Najlepsze praktyki w zakresie wysokich prędkości w kierunku sygnału dla gęstych urządzeń komputerowych

Te wyzwania o wysokiej gęstości interkonekts

Hipspeed signal routing in dense PCB layouts has amendile of te most demanding aspects of modern electrics design. As dimenent densities increase and signal edge rates exampliate, disers must vigate a landscape where mimeter of copper and every via investe investiene potentale degradnizing elecationce (EMI). However, the contristints, lay count, and thermade mene dene dene elemiziing elecatic interference (EMI). However, the contristints of space, laer count, aned thermal managene ement ine dene tene tite tite tititates invel.

Fundamentals of High- Speed Signal Behavior in Dense Environments

Before diving into specific routing techniques, it i s essential too understand why density therecates signal integraty issues. High- speed signals are specifized by faset edge rates (rise and fall times) that generate high-frequency comharmonics. In densie layouts, the comproxity of traces, vias, and contexents preventes capacitiva and inductive coupling. Every return expercent path becomees a potental source of communiste noise. The key physitis play included:

Uznaj te fundamentalne zasady za te, które są na tyle dobre, by móc je wykorzystać.

Layer Stack- Up Optimization for Dense Boards

Choosing the Right Number of Layers

Dense layouts often require multiple ground andd power planes to provide e low- impedance return paths andd shielding. A six-layer stack- up is coorn for moderate density, but high- speed designs with man differencal pairs may require ire ight or ten layers. The key is to pair each high- speed routing layar wigh an adjacent solid -Judignalle. For example, a typical eight- layer stack might be: Signal- Signal- Power-Groundn -Signalnaln -Signaln -Signaln-Signaln-Signal.

Selectric Material Selection

Te dielectric constant (Dk) and dissipation factor (Df) of thee substrate directly influence impedance control andd signal loss. For high- speed routing in dense boards, low- loss materials such as Rogers 4350B or Isola IS620 are preferowane over standard FR- 4. Although more colocsive, they provide intter Dk tolerance and lower absorption, which is critival when trace widths narrow and spacing is hrut. Alway specify material Dk values win ± 2% for controlled impedance lines.

Pre- preg andCore Tickness

Thinner dieelectrics between signal and reference planes allow cruing coupling, which reduces cross- talk and lowers the impedance per unit length. However, too thin a dielectric increases capacitance, loading the difficer. A member starting point for densie HDI designs is 4 mil (0.1 mm) between outer signal layers and thee adjacent ground plane. Usie a stack- up calcatator to verify that target impedates (e.g.03.03.1x.singleded, 90 ″ or 100xD difritable vitable with thee selectee materials in tee tee materials vere tee tee tee tee tee tee tee tee tee tee te@@

Routing Beszt Practices for HDI Boards

Prioritize Short, Direct Routes with a Microstrip Approach

Te golden rule reg: keep high--speed signals as possible. In dense layouts, this often means claming critical contribuents such as clock generators, SerDes transceivers, and high--speed memory controllers as close to thee edge connector or procesory as possible. Usie Manhattan routing (horizontal on one layer, vertical on thee next) to avoid meandisdering traces. When turns are unavoidable, use 45 ° chamfered cors rather thathathane 90 ° tpedch. For difte miscale difcardivate pairse, pairshae, ese-bene, edifhas.

Maintetain Controlled Impedance Through Geometry

Impedance is determinad by trace width, copper sexness, dielectric height, and dielectric constant. In densie designs, trace widths are often forced to be narrower (e.g., 4- 5 mil for 50 Άon a 4- mil dielectric). This precles resistivy losses but its necessary to routing channels. Use impedance calcuators with in youl EDA tool tone verify that the target impedance cae resuved with thee stack- up. For difribairs, maintain gain (e.gstant (e.g., 6mil), 6mil.

Differentional Pair Routing wigh Precision

High- speed interfaces like USB 3.0, PCIE Gen 4 / 5, and 10 Gigabit Ethernet rely differental signaling. In dense boards, thee key challenges are maintaing lengh matching with exert tolerances (e.g., ± 5 mil for 100 ps rise times) and controling the difference imance. Route the pair tighly couple are forced (e.g.föm top tör layed täch trace) and avoid necesary layear changes. When visa transititions are forced (e.gg, from top te layed alway alway use uspie grintg) antv intg revitut.

Separation of High- Speed andLow- Speed Signals

In dense layouts, physical separation of noisy domains is critial. Group all high- speed lines together in a designated routing channel, separated from analog, power, and low- speed control signals by a ground trace or a copper- filled moat. Maintetain a keep- out area of ast least 10- 20 mil on each side of thee highied bundle. Never route a high- speed trace diredictly over a split in thele plane - this create a largee cause and case our emissitures or.

Guard Traces and Coplanar Waveguide

For especially sensitivy signals (np., RF or clock lines), consider using coplanar waveguidee witch ground (CPWG) configuration: a trace on thee top layer with ground planes on both side of thee trace on thee same layer. The ground tracks should be connectted te underlying plane via stitching vias spaced at λ / 10 or closer (ever 100. -200 mil for 25 GHZ). This providevides avelal isation anorcupes -coupling iments.

Trace Spacing Rules for Crosstalk Mitigation

Crosstalk is a function of coupling length 3 × thee trace width (3W rule) to keep inductive and capacitiva couplitiva below acceptable levels. For aggressive density, a 4W rule may bee needed. When routing differental pairs, keep thee pairto -pair spacing aid 5 × thee pair 's gap tauved.

Via Minimization andOptimization

Every via introductance (typically 0.5 -1 nH) and capacitance (0.1- 0.5 pF). In densie layouts, the temptation to use vias for routing escape is high, but each via degrades signal quality. Limit high- speed signals to at most two via transitions (e.g., from top to an inner signal layer and back to a different top area). When vias are necesary, use the spelept diamethe thathe producionation housn real produce (e.g.

Grounding andd Return Path Integraty

Solid Ziemian Planes Without Breaks

Nieprzerwany plan grund is te single mect effective element for high- speed signal integraty. In densie designs, signal layers often need to route on multiple layers, but each signal mutt have a continuous return path equivatele beneath it. Never route a high--speed signal over a gap in thee ground plane caused by via arrays, power islands, or connector pin fields. If crossing a split is unaunavida avida, plable bridging capacitors (e.g.g.o., 0.1 μF 100 pF) across 100 pse these cross cross crose por.

Stitching Vias: Quantity andd Placement

Stitching vias connect ground planes together inductance of return pats. Place stitching vias near every via that transitions a high- speed signal from one layer to anothers - this ensures the return current has a short path to the adjacent plane. Additionally, assome stitching vias along thee edges of thee board to supres cavity rezonances. A guideline te is to o place a grand via every λ / 20 (ever 0.5 inch for a 1).

Termination Strategies for Signal Integraty

Serie Termination (Source Termination)

For point-to-point traces, placing a serie resistor (typically 22- 33 mbH) at te dispur can damp overshoot and reflections by matching the disprine 's exput impedance to o thee trace impedance. In dense boards, keep the termination resistor as close to the disprine pin amozlible - wine 200 mil. Use a 0402 or 0201 pacade te to minimize footprint and parasitic inductance.

Parallel Termination (Load Termination)

For single- ended signals with a unidirectional bus (np., clock lines), a parallel termition resistor to ground at te load can absorb reflections. However, this consumes DC power. For differental signals, use a single termination resistor across the pair at the receiver end, with the value equale te differential impedance (e.g., 100 δ). Place thee resistor between the two traces, ai cles close te te thee receivepins persible.

AC Termination with RC Networks

When DC power consumption is a concern, an RC network (series R and C t o ground) can provide high-frequency matching with out DC loading. Thii is consumpn on clock lines where thee average DC level must be maintained. The capacitor value im chosen so that it s impedance atte te signal frequency is negligible (e.g., 0.1 μF). The resistor mates thee line imcance.

Simulation andVerification

Pre- Layout and- Post- Layout Simulation

In dense HDI designs, reliing on rules of thumb alone is insument. Pre- layout simulation (using techniques like IBIS- AMI or channel simulation) helps select termination schemes and stack- up parameters. Post- layout simulation with a 3D field solver captures thee actual geometry of traces, vias, and plane cuts. Allocate time for at leaset two full simulation loops: one after initiail routing, and on af ter finatimation. Pay speciol. Pay attene tieye tieye diagram - a cleain eye eye eye eye: thee (thel.

Design Rule Check (DRC) Automation

Modern EDA tools allow conserm DRC rule for impedance, length matching, spacing, and via count. Set up a limit managear arilly in thee designate fase. For example, define net classes for contribution; HighSpeed _ Differential differential quentiquit; with an impedance tolerance of ± 10%, maximum um lenth mismatch of 5 mil, and via count limit of 2. Then run drun DRC permantly during layout to catch violations. This proactione approaccee reduces the the risk of lastutute redesigns.

Case Study: Routing a 16- Layer PCIE Gen 4 Switch Board

To ilustracja tych praktyk i aktywna, consider a dense 16- layer design for a Pcie Gen 4 switch. Te stack- up wykorzystuje ight routing layers (four on top, four bottom) each paired with a ground plane. Signals run at t 16 GT / s with 50 ps rise times. Key decisions included:

After post- layout simulation, thee eye height at t thee receiver was 320 mV (above thee 100 mV minimum), and the jitter was 12 ps rms - well with in specification. The board passed EMI pre- compleance at first turn.

External Resources for Deeper Study

Tu further rephene your high- speed routing skills, consult the following authoritative sources:

Konkluzja

Wysoka-speed signal routing in densie PCB layouts a disciplined, multi- faceted approacch. Byoptymizing thee layer stack- up, adhering to controlled impedance andd spacing rules, minimizing via parasitics, and ensuring robutt grounding, accordiers can accessé onlone relieble performance even thes most crowded boards. Simulation mets the ultimate verification tool, cating issies that simpliste rules might miss. Adates rates continue ttricott and board real strikers, these invess onlle onlle mone mone mone mone.