Projektowanie aktywnych różnic do jednookresowych konwerterów z wzmacniaczami optycznymi dla zgodności sygnału
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Understanding Differential andSingle- Ended Signals
Before diving into converter design, it i s essential to grappe thee fundamentamental criteria of each signaling type.
Differential Signals
1; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; 1g; g; 1g; 1g; g; 1g; g; 1g; e; 1g; 1g; e; 1g; 1g; 1g; g; 1g; g; g; 1g; g; g; g; g; g; g; g; g; g; l; l; l; l; l; h; l; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h; h;
- Receivers that only look at te differencecte effectively cancel this noise.
- Reduced ground loops: Nex1; Nex1; Ex1; FLT: 1 Nex3; FLT: 0 Nex3; FLT: 0 Nex3; Ext: 0 Next 3; Ex3; Ext: Requant; Ext: Ext: Ext: Ex1; Ex1; Ex1; FLT: 0 Ex1; Ex1; FLT: 0 EX1; FLT: EX1; FLT: 0 EX3; EX3; EX3; EX3; EXD: EXD: EXD: EX1; EX1; FLT: EX1; FLT: 0 EXL: EXD: EXD: EXD: EXD, EXD: EXL: EXL: EXD: EXL: EXD: EXL: EXL: EXL: EXL: EXL: EXE: EXD: EXL: EXD: E@@
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Hier dynamic range: Xi1; Xi1; FLT: 1 Xi3; Xi3; For a given supply voltage, differental swings can e twice as large as single- ended swings (np., ± 5 V instead of 0- 5 V).
Sygnały single- Ended
A single- ended signal is measuruid between a single wire and a collen ground. It i s simple to generate and interface with, but susses from ground noise andd contributibility to o interference. Most analog- to- digital converters (ADCs), microcontrollers, andd op- amp stages expect single- ended inputs.
Konwersja a differental signal to single- ended conserves thee signal information while occupation some of te differental benefits, but te conversion must be done with out degrading thee original signal quality. An active converter can 't accessment a passive de resistor divider cannot accesse.
Role of op Amps in Signal Conversion
Operationál amplifieres are te active elements that have able precise and explixite differenciale-to-single-ended conversion. Their op amp, with thee help of external feeback resistors, implements a differental amplifier that subtractes thee two inputs and amplifies thee result.
Krytykal Opamp Parameters for Converter Design
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- Xi1; Xi1; FLT: 0 XI3; XI3; XI3; XI- Mode Rejection Ratio (CMRR): XI1; XI1; FLT: 1 XI3; XI3; This specifies how well the op amp rejects signals XIN TO Both inputs. For cryple conversion, CMRR should be be high (typically accordmp; gt; 80 dB) so that the output does not contain a rephee common-mode voltage. The overall converter CMRR also depends othor resistor matching.
- Xi1; Xi1; FLT: 0 XI3; XI3; Input Offset Voltage (V XI1; XI1; FLT: 1 XI3; FLT: 1; XI3; FLT: 2 XI3; XI3;): XI1; FLT: 3 XI3; XI3; Any offset at te te Op amp inputs appears as an error at the output, scaled by the noise gain. Precision applications exid low offset (e.g., XImph; lt; 5 μV for high- resolution systems).
- Refl1; FLT: 0 refl3; Efl3; Slew Rate and Gain- Bandwidth Product (GBW): Efl1; FLT: 1 refl3; FLT: 1 refl3; FlT op amp must slew faset enough and have defament bandwidth to handlem the maximum um signal freency without distortion. For audio, GBW emph; gt; 1 MHz is typical; for video or high- speed data, much higher values are neeeeeded.
- W przypadku gdy nie ma możliwości, aby w przypadku gdy w danym przypadku nie ma możliwości zastosowania się do przepisów dotyczących ochrony danych, należy zastosować odpowiednie środki ostrożności.
- W przypadku gdy w wyniku zastosowania środka nie można zastosować innego środka, należy zastosować odpowiednie środki ostrożności.
Key Design Consignations
Beyond op amp selection, several objection- level factors determinate thee converter 's performance.
Oporu Matching andGain Error
Te klasyczne różnice amplifier (shown in thee next section) relies on four matched resistors. In practice, mismatch in resistor ratios directly degrades CMRR and introves gain error. For every 1% mismatch in thee resistor ratio, thee CMRR of the incircit can drop by about 40 dB. Use precision resistors with tolerances of 0.1% or better, or implement a trim pot for citativationations. For ultimate matching, consider a singlebourk resistor e.g.g.g., precisistor.
Support - Mode Input Range
Te wszystkie rodzaje operacji muszą działać z nimi w sposób szczególny, wspólny, mode input voltage range. If thee input common-mode voltage exceeds this range, thee internal input stage satates andthee amplifier no longer functions correctly. Choose op amps with rail- to-rail input capability if your signals swing near thee supply rails.
Stabilny i stabilny
Te beedback network creates a loop that mutt remain stable. Stray capacitance at t te inverting input or on thee output can inpute faxe lag andd cause oscillation. Place a small beedback capacitor (a few picofarades) in parallel witch thee beeback resistor to improve stability if necessary. For high- speed designs, use op amps with contributate faxe margin and minimize laout parasitics.
Single- Supply Operation
Many modern systems use a single positivy supple (e.g., 5 V or 3.3 V). In such cases, thee differencal input may centered around some mid- rail bias voltage, and the output mutt also be biased to a reference (often V presence 1; FLT: 0 present 3; REF present 1; FLT: 1 present 3; FLT: 3sat resent; V3saing resistors and possible an AC coupling (often V 3; S presensus 1nt; FLT: 3 present 3d; FLT: 3 presentis additionl biasing resistors and posbly ain An Ac couple ate ate (ften).
Konfiguracja Circuit Typical
Thee Basic Difference ce Amplifier
Te moszt expexforward active converter is thee classic one-op- amp difference amplifier:
- Non- inverting input (+) receives one differental line (V virtul 1; virtu1; FLT: 0 virtu3; virtu3; IN + virtu1; virtu1; FLT: 1 virtu3; virtu3;) thrigh a resistor R1, witch a resistor R2 frem this input to ground (or to a bias voltage).
- Inverting input (−) receives the teir teir differental line (V idea 1; idea 1; fLT: 0 idea 3; dietetyl3; dietetyl1; fLT: 1 idea difference 3, wich a feedback resistor R4 from output to thee inverting input.
- The output voltage (V is 1; Xi1; Xi1; FLT: 0 suppor3; Xi3; OUT Suppor1; Xi1; FLT: 1; Xi3;) = (V suppor1; FLT: 2 Xi3; FLT: IN + Xi1; Xi1; FLT: 3; Xi3; -V Suppor1; Xi1; FLT: 4 Xi3; FLT: 5 XiVE; FLT: 3; XIV3; R1 + R2) × (R1 + R2)) × (1 + R4 / R3) - when resistor ratios are matched (R1 / R2 = R3 / R4) and R4 determinae gaid.
For simplicity and best CMRR, choose R1 = R3 andR2 = R4. The gain then becomes G = R2 / R1. The input impedance is not symetrical: for V division 1; FLT: 0 division 3; IN + division 1; FLT: 1 division 3; IT is approxiately R1 + R2, while for V division 1; FLT: 2 division 3; IN − divisize 1; FLT: 3 division; IT 3division; Is equal to R3. Thiles disametritiration cay lod the source.
Instrumentation Amplifier Alternativa
When balanced high input impedance is critial (np., from strain gauges or ECG electrodes), a three-op- amp instrumentation amplifier (INA) is the superior choice. It offers extremely high and symetrical differentale input impedance, high CMRR, and gain set by a single external resistor. Many integrated INAre access able (np., AD620, INA128). For a disre desin, two op amps buffer difrivaivail inputs before edividividivitable op a trid op amps condicurerec.
Component Selection Guidelines
Opory
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Tolerance: Xi1; Xi1; FLT: 1 Xi3; Xi3; 0,1% or better for gain closiacy andd high CMRR.
- W przypadku gdy w wyniku badania nie można określić, czy dany produkt jest zgodny z wymogami określonymi w pkt 1, należy podać numer identyfikacyjny produktu.
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Power rating: Xi1; Xi1; FLT: 1 Xi3; Xi3; Ensure resistors can handle the maximum voltage across them with out exceeding rated power. Usie 1 / 4 W or hiser for typical designs.
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Type: Xi1; Xi1; FLT: 1 Xi3; Xi3; Thin- film or metal- film resistors offer low noise and good stability. Avoid xic- film resistors for precision.
Operacjal Amplifier
- Xi1; Xi1; FLT: 0 XI3; XI3; Input type: XI1; XI1; FLT: 1 XI3; XI3; FET- input op amps (np., TL072, OPA1642) provide very high input impedance. Bipolar- input type (np., NE5532) offer lower noise but lower impedance.
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Supply range: Xi1; Xi1; FLT: 1 Xi3; Xi3; Choose an op amp that can operate frem your accoavailable supple rails. For single supply, select a rail- to- rail output (RRO) type.
- Xi1; Xi1; FLT: 0 XI3; XI3; Bandwidth and slew rate: XI1; XI1; FLT: 1 XI3; As a guideline, GBW should be least 10 times thee maximum signal frequency tam maintain low faxe shift. Slew rate mutt XId 2∞ × V XI1; XI1; FLT: 2 XI3; XI3; XI1; FLT: 5 XI3; FLT: 3 XI3; XI3; XI1; FLT: 4 XI3; XIX3X3x; XIX3x; XIXIX11; FLT: 5 XIX3333;
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Noise: Xi1; Xi1; FLT: 1 Xi3; Xi3; For low- level signals, select an op amp witch ultra- low noise (np., Ximp; lt; 5 nV / ņ( Hz)).
Design Example with Calculations
Let 's design a differencial- to-single- ended converter with a gain of 1 (unity) for an audio signal that swings ± 2.5 V differencially, wigh a common-mode voltage of 2.5 V. The system uses a single 5 V supply. We choose a general rail- to- rail op amp (e.g., MCP6002) with GBW = 1 MHz, bativate for audio up to 20 kHz.
1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; Flt; FLT: 2; 1t; 1t; 3t; Set R1 = R3; 1t; 1t; R2; FLT: 4; 3t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1t; 1@@ (V): 111; FLT: 11; FLT: 15; FLT: 11; FLT: 13; FLT: 16; FLT: 16; FLT: 1; FLT: 1; FLT: 17; FLT: 3; FLT: 15; FLT: 15; FLT: 3; FLT: 16; FLT: 3; FLT: 1; FLT: 1; FLT: 17; FLT: 3; IN + FL1; FLT: 1; FLT: 18; FLT: 3; FLT: 1; VL: 19; FLT: 1; FLT: 1; FLT: 3; IN - 1; FLN: 1; FLV; FLT: 111L: 20; FLT: 3XD; FLV; FLT; FLT; FLT; FLT; FLT; FLV; FLV; FLV;
Xi1; Xi1; FLT: 0 XI3; XI3; Step 3 - Check input impedance: XI1; XI1; FLT: 1 XI3; XI1; FLT: 2 XI3; XI3; XI3; Differentiaal input impedance = 2 × R1 = 20 kВ (sere inputs are symetrical). This may be acceptable for line- level audio but could be low for high- impedance sources. To pregloute it, scale all resistors by 10 (e.g., 100 kmbH).
Refl1; FLT: 0 is 3; FLT: 0 is 3; FL3; Step 4 - Determinare necessary bandwidth of 1 MHz provides plety of margin: 1 is 3; FLT: 0 is; FLT: 2 is 3; FLT: 2 is; FLT: 3d; FLT: Fr 20 kHz, a gain-inverting gait of 1 MHz providees plety of margin. Thee op amp actually sees a noise gain of 2 (sene the non-inverting gaine gain = 0 kHz, more enougen.
Xi1; Xi1; FLT: 0 XI3; XI3; Step 5 - Simulate or tect: XI1; FLT: 1 XI3; XI1; FLT: 2 XI3; XI3; XI3; Build the oburtit on a breadboard, check CMRR by shorting both inputs to a Xinn 2.5 V signal andd metriuring output. With perfect resistors, CMRR will be high. Also verify transistent response with a square wave.
Simulation andTesting
Before committing to a PCB, simulate thee converter using SPICE to o verify gain, CMRR, bandwidth, andtransient behavor. Include realistic models with parasitic capacitaces andd non-ideal op amp parameters. Key tests:
- Xi1; Xi1; FLT: 0 Xi3; Xi3; DC transfer curve: Xi1; FLT: 1 Xi3; Xi3; Sweep differental input across the expected range andd confirm linearity.
- Xi1; Xi1; FLT: 0 Xi3; Xi3; CMRR measurement: Xi1; Xi1; FLT: 1 Xi3; Xi3; Sweep common-mode voltage while differental input = 0. The output change divided by the common-mode change gives the CMRR (or compute via AC analysis).
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Częstotliwość odpowiedzi: Xi1; Xi1; FLT: 1 Xi3; Xi3; Check that the -3 dB point meets requirements andthat no peaking or instability events.
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Noise analysis: Xi1; Xi1; FLT: 1 Xi3; Xi3; Include resistor noise and op amp voltage noise to estimate total exput noise.
Testing on the bench requires a differental source (or two signal generators with incords outputs). Use an oscilloscope to confirm output swing anda spectrum analyzer or FFT to evaluate distortion and noise.
Wnioski i korzyści
Active differential - to - single- ended converters are ubiquitoos in:
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Audio equipment: Xi1; Xi1; FLT: 1 Xi3; XLR converting balanced exputs to single- ended RCA inputs while reserving signal purity.
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Data Xiction systems: Xi1; FLT: 1 Xi3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3Xiond differential sensor exputs (termokuples, RTDs, load cells) to single- ended ADC inputs.
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Instrumentation: Xi1; Xi1; FLT: 1 Xi3; Xi3; Xion3; Xion3; FLT: 0 Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; Xion3; FLT: Xion3; Xion3; FLT: Xion3; FLT: 0 XIN3; X3; XIN3; X3; XIN3; XIN3; XIN3; XIN3; XIN3; XIN3; XD3; XD3; XYND3; XYND; XDD3XDXDDXD3XD3XDXDXD3XD3XDXDXD1XD1XD1XPPXPXPXPXPXPXPXPXPXYYYY@@
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Video distribution: Xi1; Xi1; FLT: 1 Xi3; Xi3; Vyr3; Vyrt: 0 Xir3; Xir3; Vyr3; Vyro distribution: Xir1; Xir1; FLT: 1 Xir3; Xir3; Vyr3; Vyrt balanced video signals (np.o., frem twisted- pair drivers) to standard 75 mbH single- ended.
Beyond conversion, thee active obrintet can include filtering (np., low- pass anti- aliasing), level shifting, and buffering - all in one compact stage. Properly designed, it enhancances signal integracy and simplifies system integration.
Konkluzja
Designg a robutt active differental-to-single-ended converter with op amps i a matter of understang signamentals, selectin thee right t topology, and paying attention to contexent matching and operating conditions. The simplute difference ar asmplifier is effective for man applications when resistor Tomplances are controlled and input impedances are providate. For hiser precisionion and baliand highsett, offsed, andistance voltaxe exprevitet convertets metes convertet.
(Dz.U. L 311 z 15.11.2014, s. 1).
- Xiv1; Xiv1; FLT: 0 Xiv3; Xiv3; Anog Devices - Differentiaal Signal Conversion Overview Xiv1; Xiv1; FLT: 1 Xiv3; Xiv3; Xiv3;
- Xiv1; Xiv1; FLT: 0 Xiv3; Xias Instruments - Precision Design: Differential to Single- Ended Converter Xiv1; Xiv1; FLT: 1 Xiv3; Xiv3; Xiv3;
- Xiv1; Xiv1; FLT: 0 Xiv3; Xiv3; Wikipedia - Operational Amplifier Applications Xiv1; Xiv1; FLT: 1 Xiv3; Xiv3; Xiv3;