Projektowanie sieci dystrybucji energii elektrycznej w systemie PCB dla minimalnych spadku napięcia i łączenia hałasu
Understanding Power Distribution Networks
A power distribution network (PDN) is te complete system that delivres electrical power from a source te every load on a printed object board. It conclusisses voltage regulators, traces, planes, vias, decoupling condentitors, and the interconnects between them. The primary objective of a PDN is to maindivitain a stable voltage at eaction of every active device, eddless of transistent demands. Any deviation mföne nominatage - whether drop or a highpence ripplece ripplene errcé errárárárártec, ev, evémén.
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Key Challenges in PDN Design
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Voltage drops due to resistance and impedance Xi1; Xi1; FLT: 1 Xi3; Xi3;: DC resistive losses (I × R) reduce delivered voltage; AC impedance spikes cause transient droops.
- Xiv1; Xiv1; FLT: 0 Xiv3; Xiv3; Noise coupling between signals andd power lines Xiv1; Xiv1; FLT: 1 Xiv3; Xiv3; Xiv3;: Simultanous switching noise (SSN) and power rail ripplee induche errors in sensitivy analoge or hivyspeed digital digitals.
- W przypadku gdy w ramach procedury przetargowej nie ma zastosowania żadna z poniższych technik, należy podać następujące informacje:
- Xi1; Xi1; FLT: 0 Xi3; Xi3; Keytaing signal integraty Xi1; Xi1; FLT: 1 Xi3; Xi3;: A noisy power supply degrades timing marges andd precles bit- error rates.
Thee Role of Decoupling Capacires
W przypadku gdy dane te są dostępne, należy je zweryfikować, aby zapewnić, że dane te są dostępne w systemie SIGMET.
Placement is critial: condentiors mudt be as close as possible te te power pins of thee load IC, wigh short, wige traces or direct via connections to te power plane. Every milieter of trace length adds inductance, shifting the SRF downward andd reductivenes. For the highest- difficiency decoupling (above ~ 100 MHz) cae extreme low princine - of tens (e.g., a thin laminate between powewn and planes) case expeliele low princtance - on thee ordef tens ohenries.
Strategie for Minimizing Voltage Drops
Voltage drope in a PDN have two contrigents: a DC voltage drop due te trace or plane resistance, and an AC drop due te to transident currents flowing thriumgh indictance and resistance. Minimizing both requires careful design of the power delivy path from the regulator te load.
DC Voltage Drop Reduction
Te DC resistance (DCR) of power traces and planes is inversely to- sectional area. Use thee wigesto possible traces - often a copper pour covening an entire layer - and select thicker copper (e.g., 2 oz / ft ² instead of 1 oz / ft ²) to halve thee resistance per unit length andiles ohmic wich multi- layer boards, place power and ground planet planet adjacent t layers o maximize plante anne reduce ohmic. For verhigth path (e.g.10.
AC Voltage Drop andTransient Response
Transident voltage drops occur when a load instantly drags current (np., duryng clock edge transitions or procesor wake- up). The PDN 's inductance resists changes in current, causing a voltage sag distail to distribution 1; indibul 3f: 0 message 3d; L di / dt regulator 1; FLT: 1 messat; To minimaze this, keep the sical distation fem thee voltagen module (VRM) tone the load as short aste, place bulk decouplits (e.g., 100 μF - 1 mF) near the ve vrut, ve rust, condistre, t.
IR Drop Analysis andSimulation
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Reducing Noise Coupling andEMI
Noise one the PDN couple into signal paths them impedance in both conductive and radiative mechanisms. Conductive coupling events when return contributs from multiple indicles share the same impedance in the power plane; radiative coupling stems frem large loop antens formed by the power and ground paths. A focused compect on isolation and filtering yields dramatic improwiments in overall im stem noise.
Noise Sources andCoupling Mechanisms
Te mosty, które tworzą nowe źródła energii, a PDN i s means channeous switing noise (SSN), generate when man y outputs of a digital IC switch in thee same direction at te same instant. Thee resumpting current spike flows the package andd PCB inductance, creating a voltage bounce othe power rail. This noise can couple tone via power plane itself (common -impedance coupling) or dicough adjacent signal vias (viaal -viaal).
Sygnał-to-Power Noise Isolation
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Filtering Techniques
- Reg. 1; Reg. 1; FLT: 0; FLT: 0 + 3; FLT: 0; FLT: 0 + 3; FLT: 1 + 3; FLT: 0 + 3; FLT: 0 + 3; FLT: 0 + 3; FLT: + 3; FLT: 1 + 3; FLT: + 1 + 3; FLT: + 1 + 1 + 3; FLT: + 1 + FLS: + 1 + FLS: + 1 + FLS: + 3; FLT: 0 + 3; FLT: 0 + 3; FLT: 1 +: 1 +: + 1 + FLS: 1 +: +: + 1 + FLS: +: + + + + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + FLS + 1 + 1 + 1 + 1 + FLS + FLS + 1 + D + 1 + 1 +
- Reg.
- W przypadku gdy w ramach tej procedury nie ma zastosowania żadna z poniższych technik:
PDN Design Beszt Practices
Adopting a systematic approach to PDN layout from the starte of the PCB design process saves iteracion time and improwises first-pass success. The following practices are distilled frem decades of high- speed and high- power board designs.
Layer Stack- Up Optimization
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Via Stitching i Placement
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Mierzenie i weryfikacja
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Component Selection for PDN
Choosing thee right decoupling and bulk condentitors is as important as their ir placement. The key parameters are e capacitance, rated voltage, ESR, ESL, andSRF.
- X1; FLT: 1; XI1; FLT: 0 X3; XI3; MLCCs (X5R, X7R) X1; FLT: 1 XI3; FLT: 1 XI3;: Work well for bulk andd mid- frequency decoupling (1 kHz- 100 MHz). X7R has better temperatur stabilizacyjny. Be aware of DC bias derating - capacitance can drop 50- 80% near rated voltage. Usie higher voltage rating (e.g., 10 V for a 3.3 V rail) to reduce derating.
- Xion1; Xion1; FLT: 0 Xion3; Xion3; Low- ESL MLCCs (reverse- geometrie, L- type) Xion1; Xion1; FLT: 1 Xion3; Xion3;: Offer inductance as low as 100 pH, ideal for GHz- range decoupling. Use these directly undeid BGA packages.
- Receptory: 1; FLT: 1; FLT: 0 = 3; FLT: 0 = 3; FLT: 0 = 3; FLT: 0 = 3; FLT: 0 = 3; FLT: 0 = 3; FLT: 0 = 3; FLT: 0 = 3x; FLT: 0 = 3x; Tantalum = 3x; Tantalum = 3x; Tantalum = 1; FLT: 1 = 3x; FLT: 1 = 3x; FLT: 0 = 3x = 3x; FLT: 0 = 3x = 3x; FLT = 3x; FLF = 3x; TF = 3x = 3x; TF = 3x = 3x = 3x = 3x = 3x = 3x = 3x = 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3x + 3@@
- Responses: 1; Signal 1; FLT: 0 Signal 3; Signal 3; FLT: 0 Signal 3; Signal 3; Signal 1; FLT: 0 Signal 3; FLT: 0 Signal 3; Signal 3; Signal 3; Signal 3; Electrolytic condences: Signal 1; Signal 1; FLT: 1 Signal 3; Signal 3;: Very high Capacitaance (100 μF- 1000 μF) but high ESL and limited frequency response. Suitable only for DC bulk filtering (e., input to a diversing g regulator).
A consultation rule of thumb is to place one volk capacitor (10 μF - 100 μF) per every square inch of PCB area, plus one mid- frequency cap (0.1 μF) and one high - frequency cap (10 nF) per high- speed IC. Tailor the selection to thee actual transient exirent exaid using SPICE simulations. Inviden1; end exaid 1; FLT: 0; FLT: 0; FLAS 3s applicationization nos en.1; FLT: 1; FLT: 1; FLA33provide specized specizatiof of movitov.
Konkluzja
Designing a power distribution network that delivale voltage mix noise coupling is a balancing at between DC resistance, AC impedance, dimente parasitics, and physital layout. By destabling a low target impedance across the perpedency spectrem, using optimal decoupling strategies, work form noisy and sensitivy objets, and verifying thee dimengh simulation and metrimerement, dicers cate cute PNs thatt supt reliable, hiperfore trecics.