Introduction

Quantum computing aims to exploit quantum mechanical phenomena to perform calculations beyond the reach of classical machines. A central challenge in building a practical quantum computer is constructing stable, scalable qubits that can be fabricated with semiconductor manufacturing techniques. Semiconductor nanowires—high‑aspect‑ratio structures with diameters typically below 100 nm—have emerged as a leading platform for qubit implementation. Their geometry confines electrons or holes in one‑dimensional channels, creating discrete energy levels that can be used as qubit states. In addition, nanowires can be grown epitaxially on silicon substrates, offering a path toward integration with existing microelectronics. Over the past decade, advances in fabrication methods such as molecular‑beam epitaxy, vapor‑liquid‑solid growth, and bottom‑up chemical assembly have dramatically improved the purity, uniformity, and quantum coherence of nanowire devices. This article reviews the latest developments in semiconductor nanowire fabrication for quantum computing, highlights material‑specific challenges, and discusses the roadmap toward fault‑tolerant quantum processors.

The Role of Semiconductor Nanowires in Qubit Realization

Semiconductor nanowires provide a versatile platform for several qubit architectures. Their narrow cross‑section and high surface‑to‑volume ratio allow precise electrostatic gating, which is essential for defining quantum dots and controlling tunnel couplings. Moreover, the material composition of nanowires can be varied along their length, creating heterostructures that confine carriers in both dimensions. This flexibility has enabled demonstration of spin qubits, valley qubits, and topological qubits.

Qubit Host Architectures

  • Spin qubits in quantum dots: Nanowire quantum dots formed by applying voltages to gate electrodes trap individual electrons or holes. The spin degree of freedom of a single carrier serves as the qubit. Recent work using InAs nanowires has achieved spin coherence times exceeding tens of microseconds and single‑qubit gate fidelities above 99.9%.
  • Topological qubits (Majorana zero modes): When a nanowire with strong spin‑orbit coupling is placed in proximity to a superconductor and subjected to a magnetic field, Majorana bound states can appear at the wire ends. These non‑Abelian anyons are protected against local decoherence, making them promising for fault‑tolerant computation. InSb and InAs nanowires have been the primary materials for Majorana experiments.
  • Charge qubits and Gatemon qubits: Nanowires can also form superconducting qubit variants such as the gatemon, where a semiconducting nanowire Josephson junction provides tunability via a gate voltage.

Advantages Over Other Platforms

Compared to superconducting qubits or trapped ions, semiconductor nanowire qubits offer several unique benefits. Their size allows dense integration—potentially millions of qubits on a single chip. Because they are fabricated using established planar processes, they can leverage the scalable infrastructure of the silicon semiconductor industry. Furthermore, the ability to engineer the nanowire’s band structure and spin‑orbit coupling through materials design provides a knob to tailor qubit properties. Finally, nanowire qubits can operate at temperatures above 1 K (for certain designs), easing the cryogenic requirements.

Advances in Fabrication Techniques

The past five years have seen rapid progress in nanowire growth and processing. Several key techniques have pushed the boundaries of quality and reproducibility.

Molecular Beam Epitaxy (MBE)

MBE is the gold standard for growing high‑purity III‑V nanowires. In this method, beams of elemental atoms (e.g., indium, arsenic, antimony) are directed at a heated substrate under ultra‑high vacuum. By controlling the flux ratios and substrate temperature, researchers can grow defect‑free nanowires with atomically abrupt interfaces between materials. Recent advances include the growth of core‑shell nanowires where an inner semiconducting core is wrapped by a wider‑bandgap shell. The shell reduces surface scattering and improves electrical transport, critical for qubit coherence. For example, InAs/InAlAs core‑shell nanowires fabricated by MBE have shown mean free paths exceeding 1 µm and vastly reduced charge noise compared to bare InAs wires. (See Krogstrup et al., Nano Lett. 15, 273 (2015)).

Vapor‑Liquid‑Solid (VLS) Growth

In the VLS process, a metal catalyst droplet (often gold) is deposited on a substrate and heated in a reactor with precursor gases. The precursors dissolve into the liquid droplet, and upon supersaturation, a solid nanowire precipitates beneath the droplet. VLS allows precise control over nanowire diameter (set by the catalyst size) and length (via growth time). Innovations in VLS include the use of alternative catalysts such as indium or bismuth to avoid gold‑related deep‑level traps that degrade quantum properties. Using gold‑free VLS, groups have grown InSb nanowires with mobilities exceeding 5×10⁴ cm²/V·s, which is essential for observing ballistic transport and Majorana signatures. Recent work demonstrates that in situ catalyst engineering can produce atomically smooth nanowire surfaces, further reducing disorder (see Gazibegović et al., Nat. Nanotechnol. 13, 1073 (2018)).

Selective Area Growth (SAG)

SAG is an alternative approach that does not require a catalyst. A mask (typically SiO₂ or SiN) is patterned on the substrate, and nanowires grow only in the exposed openings via metal‑organic vapor phase epitaxy (MOVPE). SAG enables precise placement of nanowires at predetermined positions, a requirement for scaled‑up integration. It also avoids metal contamination. Researchers have used SAG to create vertical arrays of nanowires with uniform diameters and controlled crystal phases. For quantum computing, SAG is particularly attractive because it allows seamless integration with conventional CMOS processing. Recent results show that SAG‑grown InAs nanowires exhibit similar transport quality to VLS wires, with low‑temperature contact resistances below 100 Ω (see Fasth et al., Nano Lett. 21, 3537 (2021)).

Bottom‑Up Assembly and Chemical Synthesis

Bottom‑up techniques use chemical reactions in solution to grow nanowires without a catalyst. Colloidal nanowires can be produced in large quantities and then assembled onto substrates via dielectrophoresis or Langmuir‑Blodgett methods. Although the level of crystallinity is often lower than epitaxially grown wires, recent advances in colloidal synthesis of CdTe and InP nanowires have yielded single‑crystalline structures with lengths up to 10 µm. These wires can be deposited on arbitrary substrates, including flexible ones, opening the door to hybrid quantum devices that combine semiconductor nanowires with superconducting resonators on a chip. While not yet competitive for high‑fidelity qubits, bottom‑up methods are promising for rapid prototyping and for exploring new materials not easily grown by MBE or VLS.

Material Considerations for Quantum Coherence

The choice of semiconductor material strongly impacts qubit performance. Key figures of merit include the effective g‑factor, spin‑orbit coupling strength, electron effective mass, and the density of nuclear spins (which cause hyperfine dephasing).

III‑V Semiconductors

Indium arsenide (InAs) and indium antimonide (InSb) are the most extensively studied III‑V nanowire materials for quantum computing. Both have small effective masses (0.023 m₀ for InAs, 0.014 m₀ for InSb), leading to large subband spacings and strong confinement. They also exhibit high g‑factors (≈15 for InAs, ≈50 for InSb), facilitating spin manipulation with microwave fields. The strong spin‑orbit interaction in these materials is essential for spin‑orbit qubits and for creating topological superconductivity. However, III‑V nanowires suffer from surface states that induce charge noise and limit coherence. Advanced passivation strategies, such as in situ deposition of a high‑k dielectric (Al₂O₃ or HfO₂) via atomic layer deposition, have been shown to reduce low‑frequency charge noise by up to two orders of magnitude (see Phys. Rev. Applied 12, 034035 (2019)).

Silicon and Germanium

Silicon and germanium nanowires offer the advantage of a mature, low‑disorder material system with no nuclear spins in the most abundant isotopes (²⁸Si, ⁷⁰Ge). This virtually eliminates hyperfine decoherence, yielding spin qubits with coherence times exceeding seconds in isotopically purified silicon. Although the spin‑orbit coupling is weaker than in III‑Vs, researchers have devised ways to manipulate spins using electric dipole spin resonance via a micromagnet or a gradient field. Germanium, especially the Ge/SiGe heterostructure, has recently gained attention because of its high hole mobility and strong spin‑orbit coupling in the valence band. Hole spin qubits in germanium nanowires have shown promise for p‑type quantum computing. Challenges for Si and Ge nanowires include achieving low contact resistance (especially for holes) and integrating them with superconductors for topological experiments. Nonetheless, the compatibility with industrial silicon fabrication makes Si and Ge nanowires a compelling choice for scalable quantum computing.

Overcoming Challenges: Defects, Disorder, and Integration

Despite the impressive progress, several hurdles remain before nanowire‑based quantum computers can be built at scale.

Reducing Charge Noise and Traps

Charge noise from fluctuating defects in the oxide or at the nanowire surface is one of the primary decoherence sources. In recent years, researchers have developed ultra‑clean dielectric deposition processes that dramatically lower the noise level. For example, using a crystalline oxide (e.g., Al₂O₃ grown by atomic layer deposition) on InAs nanowires has reduced the charge noise spectral density to below 10⁻¹⁶ e²/Hz at 1 Hz. Another approach is to use a screening layer, such as a conductive gate that is kept at a constant voltage to minimize surface potential fluctuations. Furthermore, the growth of core‑shell structures with a wide‑bandgap shell (e.g., InAs/GaAsSb) effectively moves the electron wave function away from the surface, mitigating surface‑related traps.

Nanowire Placement and Circuit Integration

Scalability requires that nanowires be positioned precisely on a chip with alignment to pre‑fabricated gate electrodes and superconducting resonators. SAG inherently addresses this issue, but other methods rely on transfer techniques. For example, a single nanowire can be picked up from a growth substrate using a micromanipulator and placed onto a target chip with sub‑micrometer accuracy. In parallel, researchers have developed self‑assembly approaches using DNA origami or dielectrophoresis to align nanowires in parallel arrays. A major step forward came from the demonstration of a 4×4 cross‑bar array of InAs nanowires with individual gate control, each hosting a quantum dot that could be read out by a charge sensor (see Nature 584, 545 (2020)). This level of integration is a prerequisite for multi‑qubit operations in a quantum processor.

Future Directions: Topological Qubits and Beyond

The most far‑reaching goal of semiconductor nanowire fabrication is the realization of topological qubits that are intrinsically protected from decoherence. Majorana bound states (MBS) are predicted to occur in a nanowire with strong spin‑orbit coupling when placed in contact with an s‑wave superconductor and a magnetic field along the wire axis. Since their theoretical proposal, hundreds of experiments have reported signatures consistent with MBS, yet conclusive proof remains elusive. The main obstacle is disorder—even a small amount of potential fluctuations along the wire can mimic Majorana signatures. Recent advances in nanowire quality—through improved growth, cleaner interfaces, and better superconductor deposition (e.g., in situ shadow‑mask techniques to deposit Al onto InSb nanowires)—have reduced the disorder length scale to below 100 nm. Theoretical work suggests that with mobility above 10⁵ cm²/V·s and sub‑micrometer uniformity, the observation of quantized conductance at zero bias (the “smoking gun” for Majoranas) should be possible.

Beyond Majoranas, nanowires are also being explored for braiding operations using electronic interferometry and for encoding qubits in the parity of two spatially separated Majorana pairs. This would require networks of nanowires connected in arrays—akin to a quantum version of a classical circuit. Fabrication of such complex geometries is underway using SAG and electron‑beam lithography to create Y‑branched wires and quantum‑dot‑based electron‑turnstiles.

Other emerging directions include the use of two‑dimensional materials such as transition‑metal dichalcogenides (e.g., MoS₂, WS₂) as the nanowire material itself (though typically studied as flakes, they can be rolled into nanotubes) or as a gate dielectric for conventional nanowires. Additionally, the combination of nanowires with superconducting circuits has led to the “gatemon” qubit, which combines the tunability of a semiconducting junction with the long coherence of a superconducting transmon. In 2023, a team at TU Delft reported a gatemon qubit with T₁ above 100 μs, rivaling conventional transmons.

Conclusion

Semiconductor nanowire fabrication has undergone a revolution over the last decade, transitioning from proof‑of‑concept experiments to devices that routinely achieve coherence times in the microsecond range and gate fidelities above 99.9%. MBE, VLS, and SAG growth techniques now yield nanowires with minimal defects, high mobilities, and precisely controlled dimensions. By choosing appropriate materials (III‑Vs for spin‑orbit qubits and Majoranas; Si/Ge for ultra‑long spin coherence), researchers can tailor the qubit’s properties to their specific architecture. The remaining challenges—charge noise, placement accuracy, and material uniformity—are being addressed through innovative passivation schemes, in situ metrology, and integration with CMOS‑compatible processes. With continued progress, semiconductor nanowire‑based quantum processors could become a reality within the next ten years, unlocking computational power beyond the reach of classical machines. For the latest updates on this rapidly evolving field, readers are encouraged to follow journals such as Nature Materials and Physical Review B, which regularly publish critical advances in nanowire fabrication and quantum computing.