Introduction to Active Peak Hold Circuits

Capturing the maximum value of a transient signal with high fidelity is a recurring challenge in electronic measurement and instrumentation. Whether you are analyzing a glitch on a power rail, measuring the peak amplitude of a pulse from a photodetector, or characterizing the envelope of an RF burst, you need a circuit that can track a rapidly changing voltage and store its highest excursion for subsequent processing. Active peak hold circuits, built around operational amplifiers (op amps), provide a robust, repeatable, and accurate solution to this problem. By combining the precision of active feedback with the memory function of a storage capacitor, these circuits overcome the limitations of passive diode-capacitor peak detectors, delivering low droop, high input impedance, and fast acquisition times.

This article provides a comprehensive guide to designing active peak hold circuits with op amps. We cover the fundamental operating principles, compare various topologies, discuss component selection and sizing, and examine critical trade-offs such as acquisition speed versus droop rate. Practical implementation examples and advanced techniques—including multiple peak capture and auto-reset mechanisms—are presented to help you integrate these circuits into real-world measurement systems. Throughout the discussion, we reference authoritative resources from Analog Devices and Texas Instruments for deeper technical dives. By the end, you will have the knowledge to design a peak hold circuit tailored to your specific transient signal capture requirements.

The Principle of Peak Detection and Hold

A peak hold circuit performs two sequential functions: detection and storage. During detection, the circuit continuously compares the instantaneous input voltage against a stored reference. When the input exceeds the reference, the circuit updates the storage element—typically a capacitor—to the new input level. During the hold phase, the capacitor retains the peak voltage, isolated from the input and from the load that reads the output. The challenge is to make the transition from detection to hold both fast and accurate, and to maintain the stored voltage with minimal drift over the observation window.

In a passive implementation, a diode and capacitor form a simple peak detector. The diode charges the capacitor to the peak of the input waveform, but the diode forward voltage drop (typically 0.6–0.7 V for silicon) introduces a systematic error, and the reverse leakage of the diode causes droop. Active circuits eliminate the diode drop error by placing the diode inside the feedback loop of an op amp, effectively canceling its threshold voltage. Additionally, the high input impedance of the op amp minimizes loading on the signal source, while a buffer op amp at the output prevents the load from discharging the hold capacitor.

Active vs. Passive Peak Hold: A Comparative View

Before diving into circuit design, it is instructive to compare active and passive peak hold approaches. Passive peak detectors are simple and inexpensive, but they suffer from several drawbacks: the forward voltage drop of the diode limits accuracy for low-level signals, and the output voltage cannot reach the true peak without compensation. Moreover, the input impedance is not constant—it varies with signal level—and the reverse recovery time of the diode can limit high-speed performance.

Active peak hold circuits, in contrast, use op amps to provide near-ideal diode characteristics. The op amp boosts the effective gain around the diode, reducing the apparent forward drop to microvolt levels. The input stage of the op amp presents a high and stable input impedance, typically tens of megaohms for JFET-input types and even higher for CMOS-input types. The output buffer isolates the hold capacitor from downstream circuitry, virtually eliminating loading-induced droop. These advantages make active circuits the preferred choice for precision instrumentation, data acquisition, and automatic test equipment (ATE) where accuracy and repeatability are critical.

Core Op-Amp Peak Hold Topologies

The Classic Diode-Capacitor Configuration

The simplest active peak hold circuit places a diode and capacitor in the feedback path of an op amp. The input signal drives the non-inverting input of the op amp. The op amp output drives the anode of a diode, whose cathode is connected to the hold capacitor and also to the inverting input for negative feedback. When the input voltage rises, the op amp output increases, forward-biasing the diode and charging the capacitor until the voltage at the inverting input matches the input. When the input falls, the op amp output swings low, reverse-biasing the diode, and the capacitor retains its voltage. A buffer op amp with high input impedance reads the capacitor voltage without discharging it.

This topology is straightforward, but it has limitations. The op amp must source enough current to charge the capacitor quickly when a new peak arrives, which demands adequate slew rate and output current capability. During the hold phase, the op amp output goes into saturation near the negative rail, and its recovery time when a higher peak appears can introduce delay. Despite these issues, this configuration works well for moderate-speed signals (up to tens of kilohertz) with careful component selection.

Precision Rectifier-Based Peak Hold

To improve accuracy, a precision rectifier can replace the simple diode. In this topology, a second op amp is configured as an ideal half-wave rectifier, with the diode placed inside the feedback loop. The output of the rectifier drives the hold capacitor through a resistor or directly. The feedback forces the rectifier output to follow the input exactly during the charging phase, virtually eliminating the diode drop. The hold capacitor sees a voltage that is exactly the input peak, minus only the op amp offset voltage and any leakage currents.

Precision rectifier-based peak hold circuits offer significantly better accuracy than the classic configuration, especially for low-level signals where a diode drop would be a large fraction of the peak. They are widely used in precision AC-to-DC converters, audio level meters, and medical instrumentation. However, the added op amp and feedback complexity increase design effort and may reduce the maximum operating frequency due to loop stability considerations.

High-Speed Track-and-Hold Architectures

For very fast transient signals—those with rise times in the nanosecond range—conventional op-amp peak hold circuits may be too slow. In these cases, a track-and-hold (T/H) architecture is more appropriate. A T/H circuit uses a high-speed switch (typically a JFET or analog switch) in series with the hold capacitor, controlled by a comparator. The comparator monitors the input against the held output; when the input exceeds the output, the switch closes (track mode), charging the capacitor to follow the input. When the input drops below the output, the comparator opens the switch (hold mode).

Modern integrated T/H amplifiers, such as the AD783 or AD9100 from Analog Devices, incorporate these functions in a single package with acquisition times as low as a few nanoseconds. Discrete implementations using high-speed comparators (like the LMH7322 from Texas Instruments) and RF switches can achieve even higher performance for specialized needs. The trade-off is increased design complexity, power consumption, and sensitivity to parasitic capacitance and PCB layout.

Component Selection and Sizing

Choosing the right components is essential for a successful active peak hold design. The key elements are the op amp, the hold capacitor, the diode (if used), and the reset mechanism.

Op-Amp Selection Criteria

The op amp used in the peak detection stage must have a slew rate and bandwidth adequate for the fastest transient you expect to capture. As a rule of thumb, the op amp's small-signal bandwidth should be at least ten times the highest frequency component of the input signal. For example, capturing a 1 µs pulse (approximately 1 MHz bandwidth) requires an op amp with at least 10 MHz gain-bandwidth product and a slew rate of 10 V/µs or more for a 5 V peak output. JFET-input op amps such as the TL07x or OPA2134 offer high input impedance and low bias current, making them suitable for moderate-speed designs. For higher speeds, consider the LMH6657 (200 MHz, 600 V/µs) or the ADA4897 (200 MHz, 800 V/µs) from Analog Devices. A second op amp used as a buffer should have low input bias current to minimize capacitor discharge during the hold phase; the same JFET-input types work well here.

Hold Capacitor Considerations

The hold capacitor (C_HOLD) is the memory element. Its value determines the trade-off between acquisition time and droop rate. A smaller capacitor charges faster, enabling the circuit to capture brief transients, but it also droops faster due to leakage currents. A larger capacitor holds the peak longer but requires more current from the op amp to charge. Typical values range from 100 pF for nano-second-scale signals to 10 µF for low-frequency applications. Choose a capacitor with low dielectric absorption (e.g., polypropylene, polystyrene, or C0G/NP0 ceramic) to minimize memory effects. For high-precision measurements, use a capacitor with a leakage specification—such as a low-leakage film type—and consider that the input bias current of the buffer op amp also contributes to droop.

Diode and Switch Choices

In circuits that use a diode for direction control, select a fast-switching diode with low reverse leakage, such as a Schottky diode (e.g., BAT54 or 1N5711). Schottky diodes have a lower forward voltage drop (around 0.3 V) than standard silicon diodes, which reduces the burden on the op amp feedback loop. For high-voltage designs, use a fast recovery diode with appropriate voltage rating. If you are using a track-and-hold architecture with a discrete switch, choose an analog switch with low on-resistance, low charge injection, and high off-isolation, such as the ADG1419 or TS12A12511.

Design Trade-Offs and Performance Optimization

Every peak hold circuit involves fundamental trade-offs that you must manage to meet your application requirements.

Droop Rate and Leakage

Droop is the gradual decay of the held voltage due to leakage currents from the hold capacitor, the input bias current of the buffer op amp, and the reverse leakage of any protection diodes. The droop rate (in V/s) is given by I_LEAK / C_HOLD. To reduce droop, you can increase C_HOLD (at the cost of longer acquisition time) or minimize leakage. Using a JFET or CMOS buffer op amp with an input bias current in the picoamp range is essential. Also, physically guard the hold capacitor node by surrounding it with a driven shield at the same potential to minimize PCB surface leakage.

Acquisition Time vs. Overshoot

Acquisition time is the interval from when a new peak appears at the input to when the hold capacitor settles to within a specified error band around that peak. A smaller capacitor and a higher charging current reduce acquisition time. However, aggressively charging the capacitor through the op amp can cause overshoot, which then requires settling time. Adding a small series resistor (10–100 Ω) between the diode and the capacitor can damp the charging transient and reduce overshoot at the expense of slightly longer acquisition. In precision applications, a trade-off between acquisition speed and settling accuracy is inevitable.

Bandwidth and Slew Rate Limits

The finite bandwidth and slew rate of the op amp create a delay between the input and the held output. For a sinusoidal input, the peak of the output will lag the true input peak by an amount related to the phase shift through the op amp. For pulses, the limited slew rate means the op amp cannot charge the capacitor instantly, so the held peak will be lower than the true peak if the pulse is very short. To mitigate this, overspecify the op amp bandwidth and slew rate by a factor of three to five relative to the fastest input transient.

Practical Implementation Example

Circuit Description

Consider a practical design targeting a 10 V peak pulse with a rise time of 1 µs. The circuit uses a classic active peak hold with a Schottky diode. The input op amp is an OPA2134 (8 MHz, 20 V/µs, JFET input) configured as a voltage follower with the diode in the feedback path. The hold capacitor is 1 nF (C0G ceramic), which gives a reasonable compromise between acquisition and droop. The buffer is a second OPA2134 rail-to-rail output stage. A reset switch (an N-channel JFET, such as the J201) is connected across C_HOLD and is driven by a digital signal to discharge the capacitor between measurements.

In operation, when a positive-going pulse arrives at the input, the OPA2134 output rises quickly, forward-biasing the Schottky diode (BAT54) and charging the 1 nF capacitor. The voltage at the inverting input follows the input. After the pulse peak passes, the diode reverse-biases, and the buffer op amp presents the held voltage to the output with negligible loading. The droop rate, dominated by the OPA2134 input bias current (5 pA typical), is approximately I/C = 5 pA / 1 nF = 5 mV/s, which is acceptable for a hold time of 100 ms. The acquisition time for a 10 V step is roughly (C * ΔV) / I_CHARGE. With the OPA2134 capable of sourcing 25 mA, charging 1 nF by 10 V takes about 0.4 µs, plus a small settling time.

Simulation and Measurement Insights

SPICE simulations of this circuit show that the held output captures 99.9% of the true peak within 2 µs for a 1 µs rise-time pulse. The droop over 100 ms is 0.5 mV, consistent with the leakage calculation. Measurement on a prototype using a two-layer PCB with proper grounding and guard traces around the hold capacitor node yields similar results. The main discrepancy between simulation and measurement comes from PCB surface leakage, which can add tens of picoamps of current if the board is not cleaned thoroughly. In high-humidity environments, a conformal coating on the hold node dramatically improves droop performance.

Advanced Techniques

Multiple Peak Capture

Some applications require capturing the peaks of a train of pulses or the local maxima of a waveform. A single peak hold circuit holds only the global maximum since its last reset. To capture multiple peaks, you can cascade a peak hold with a sample-and-hold and a logic controller that stores each peak in sequence. Alternatively, use a digital peak detection approach: a high-speed ADC samples the waveform and a field-programmable gate array (FPGA) or microcontroller performs peak-finding in software. For analog-domain solutions, a switched-capacitor array can store multiple peaks, but the complexity increases rapidly.

Reset and Auto-Reset Mechanisms

Many measurement systems require the peak hold to reset automatically after a readout. A common method is to place a JFET or analog switch in parallel with the hold capacitor. When the reset signal goes high, the switch turns on, shorting the capacitor to ground (or to a reference voltage) and discharging it. After a brief delay, the switch turns off, and the circuit is ready to capture a new peak. For automatic operation, a timer circuit or a microcontroller can generate the reset pulse after each measurement cycle. Ensure the switch has low off-leakage to avoid additional droop during the hold phase.

Differential Peak Hold

In applications such as balanced signal transmission or current sensing across a shunt resistor, you may need to capture the peak of a differential signal. A differential peak hold circuit uses two identical peak hold stages, one for the positive signal and one for the negative signal (or a differential amplifier feeding a single peak hold). The output is the difference between the two peaks. This topology preserves the common-mode rejection of the front-end amplifier while enabling peak detection of fast differential transients. High-speed differential peak hold circuits are used in power electronics for measuring voltage spikes across switching devices and in medical ultrasound front-ends for envelope detection.

Applications in Detail

Active peak hold circuits are ubiquitous in measurement and instrumentation. In oscilloscopes, peak detection and hold are used for envelope mode, where the display shows the maximum and minimum signal amplitude over time, enabling the visualization of rare events. In automatic test equipment (ATE), peak hold circuits measure the transient response of devices under test, such as the peak power of an RF amplifier or the overshoot on a digital line. In power supply testing, they capture the peak voltage ripple and transients during load steps. In medical devices, such as defibrillator analyzers and patient monitors, peak hold circuits capture the amplitude of physiological signals like ECG R-waves or pulse oximeter waveforms. In audio analysis, they provide a peak-reading VU meter that responds to brief transients, giving a realistic indication of signal level.

The choice of topology and component values depends on the signal characteristics: for audio, a precision rectifier-based peak hold with a time constant of tens of milliseconds is standard; for RF, a high-speed track-and-hold with a Schottky diode and a small hold capacitor (100 pF) is common. For detailed design examples, refer to Analog Devices application note AN-71, "A Precision Peak Detector," and Texas Instruments application report SBAA127, "Peak Detector Circuit Concepts."

Conclusion

Active peak hold circuits using op amps provide a flexible, accurate, and repeatable solution for capturing transient signal peaks. By understanding the core design principles—diode placement within the feedback loop, capacitor selection, and buffer isolation—you can build circuits that achieve high precision over a wide range of signal speeds and amplitudes. The trade-offs between acquisition time, droop, overshoot, and bandwidth must be managed through careful component selection and circuit layout. Advanced techniques such as auto-reset, multiple peak capture, and differential peak hold extend the utility of these circuits into specialized measurement domains. Whether you are designing bench instrumentation, embedded sensors, or production test systems, the active peak hold remains an indispensable building block. For further exploration, consult the references from Analog Devices and Texas Instruments, and prototype on a clean PCB with guard traces to maximize performance. With these tools, you can reliably capture the transient events that matter in your electronic designs.