Designing High-input Impedance Buffer Circuits with Op Amps for Sensitive Signal Sources

Understanding High-Input Impedance Buffer Circuits

High-input impedance buffers are fundamental building blocks in analog signal conditioning. Their primary role is to prevent a sensitive signal source from being loaded down by the downstream circuitry. When a source has high output impedance (e.g., a pH probe, piezoelectric sensor, or high-gain photodiode amplifier), even a modest load resistance can attenuate the signal or introduce nonlinearities. A buffer with an input impedance in the gigaohm range and an output impedance near zero effectively isolates the source, allowing the signal to be transmitted without degradation.

The classic voltage follower (unity-gain buffer) achieves this by using negative feedback to make the output voltage precisely track the input voltage. Operational amplifiers (op amps) with extremely high open-loop gain make this possible. The non-inverting input presents the high impedance, while the inverting input receives the feedback signal, ensuring the output drives the load independently of the source.

Selecting the Right Operational Amplifier

Not all op amps are suitable for high-impedance buffers. The key parameters to evaluate include input impedance, input bias current, input offset voltage, bandwidth, and noise. For sensitive sources, the input bias current is often the most critical—it must be low enough that the voltage drop across the source's output resistance does not cause an unacceptable offset or drift. JFET-input and CMOS-input op amps are the standard choices because their input bias currents are typically in the picoamp range.

Parameter	Typical Requirement for Sensitive Sources
Input Impedance	≥ 10¹² Ω (JFET/CMOS)
Input Bias Current	≤ 100 pA (ideally < 10 pA)
Input Offset Voltage	< 1 mV for DC accuracy
Gain-Bandwidth Product (GBW)	10× the maximum signal frequency
Noise (1/f and broadband)	Low for low-level signals

JFET vs. CMOS Op Amps

JFET-input op amps such as the TL081, LF356, or OPA140 offer very high input impedance (10¹² Ω) and low noise at moderate frequencies. Their bias currents increase with temperature, which can be a concern in some applications. CMOS-input op amps like the LMP7721, OPA333, or ADA4522 achieve even lower bias currents (femtamperes at room temperature) and often feature rail-to-rail inputs and outputs, making them ideal for single-supply designs. However, CMOS op amps typically have higher flicker noise at low frequencies; if the signal bandwidth is below 100 Hz, a JFET part may provide better noise performance.

Bipolar Op Amps are Generally Unsuitable

Bipolar op amps (e.g., LM741, NE5532) have input bias currents in the microamp range, which creates unacceptable voltage drops across any significant source resistance. For a 1 MΩ source impedance, a 100 nA bias current produces a 0.1 V error, completely swamping a microvolt-level sensor signal. Therefore, always choose JFET or CMOS for high-impedance buffers.

Design Principles of the Unity-Gain Buffer

The canonical circuit is straightforward: the input signal connects to the non-inverting input (+), and the output is directly wired to the inverting input (−). This negative feedback forces the op amp to drive the output until the voltage at the inverting input equals the input voltage. The resulting closed-loop gain is ideally 1.000, with any deviation caused by finite open-loop gain being negligible (errors are typically less than 0.01% for modern op amps).

While simple, the buffer demands careful attention to stability, especially when driving capacitive loads. The op amp's output stage and feedback loop may oscillate if the load capacitance exceeds a certain limit. Most data sheets specify the capacitive load handling capability and recommend adding a small resistor (e.g., 10–50 Ω) in series with the output to isolate the load.

Practical Component Values

No external resistors are required for the basic follower, but two additional components are nearly always necessary:

Input protection resistor: A 1 kΩ to 10 kΩ resistor in series with the non-inverting input can limit fault current if the input voltage exceeds the supply rails. This resistor adds negligible noise and only slightly reduces input impedance (still >10⁹ Ω).
Feedback resistor (optional): Some designers insert a small resistor (e.g., 50 Ω) in the feedback path from output to inverting input to improve stability when driving heavy loads. This is not needed for most CMOS op amps but can be useful for high-speed JFET types.

Power Supply and Decoupling

High-impedance buffers are extremely sensitive to power supply noise. Any ripple or noise on the supply rails couples into the signal through the op amp's power supply rejection ratio (PSRR). Although modern op amps have excellent PSRR (80–120 dB) at DC, PSRR degrades at higher frequencies. Proper decoupling is essential:

Place a 0.1 µF ceramic capacitor as close as possible to each supply pin (V+ and V−).
Add a 10 µF electrolytic or tantalum capacitor in parallel for lower frequency bypassing.
Use separate analog and digital supply traces if the buffer shares a board with digital circuits.
Consider using a low-noise voltage regulator (e.g., LP5907 or TPS7A49) to supply the op amp.

Minimizing Input Bias Current Effects

Even JFET and CMOS op amps have some input bias current, which flows through the source impedance and creates an offset voltage. For a 1 MΩ source and 10 pA bias current, the offset is 10 µV—acceptable for many applications. But if the source impedance is 100 MΩ, the same bias produces 1 mV, which may be problematic. To mitigate this:

Use an op amp with guaranteed low input bias current at the operating temperature.
Keep PCB traces from the input to the op amp as short as possible to minimize leakage currents from dirt or moisture.
Include a guard ring around the input pin: a copper trace driven by the same voltage as the input (easy for a buffer, since both inputs are at the same potential) that shunts leakage currents away from the sensitive node.
In extreme cases, apply a bootstrap technique where the guard drive is actively controlled.

Guard Ring Example: For a surface-mount op amp, the guard is a narrow trace surrounding the input pin, connected to a low-impedance node at the same voltage (e.g., output through a buffer). This reduces surface leakage by a factor of 10–100.

Noise Considerations in High-Impedance Buffers

The buffer itself adds noise to the signal. The total noise at the output depends on the op amp's voltage noise density, current noise density, and the source impedance. At high impedances, the current noise (in) flowing through the source impedance produces a voltage noise term (in × Zsource) that often dominates. Therefore, choosing an op amp with low current noise is critical. JFET op amps typically have current noise in the fA/√Hz range, while CMOS parts may be slightly higher.

For example, the OPA140 (JFET) has a current noise of 1 fA/√Hz; with a 10 MΩ source, this yields 10 nV/√Hz thermal noise. The op amp's voltage noise (5.1 nV/√Hz) then dominates. A CMOS op amp like the LMP7721 has 4.7 nV/√Hz voltage noise and 0.2 pA/√Hz current noise, which at 10 MΩ gives 2 µV/√Hz—much worse. Hence, for high source impedances, JFET op amps often provide a noise advantage despite their higher voltage noise.

Designing for Minimum Noise

Match the source impedance to the op amp's noise resistance to achieve the lowest noise figure.
Use a low-pass filter at the buffer output to restrict bandwidth to the signal's highest frequency—this reduces total integrated noise.
Keep the ambient temperature low; resistor thermal noise (√4kTR) scales with temperature.
Choose resistors with low excess noise (metal film), especially in the feedback network if used.

Stability and Capacitive Loads

Many high-impedance sensors are connected to the buffer through a long cable, which adds significant capacitance. If the op amp cannot drive the cable's capacitance without oscillation, the system becomes unusable. To maintain stability:

Consult the op amp data sheet for the maximum capacitive load it can drive at unity gain.
If the load capacitance exceeds the limit, insert a small resistor (Riso) in series with the output, typically 20–100 Ω. This isolates the capacitive load and adds a zero in the transfer function, improving phase margin. The trade-off is a slight increase in output impedance at high frequencies.
Alternatively, use an op amp specifically designed for high capacitive load drive, such as the OPA2192 or the LT6220.
Add a small feedback capacitor (e.g., 1–10 pF) in parallel with the direct feedback connection to roll off the loop gain at high frequencies and prevent oscillation.

Layout Best Practices for High-Impedance Nodes

The physical layout can make or break a high-impedance buffer. Leakage currents from adjacent traces, parasitic capacitance, and noise pickup become significant when the input impedance exceeds 10 MΩ. Follow these guidelines:

Minimize trace length: Keep the input trace as short as possible. If the signal source is external, use a shielded cable with a driven guard (active guard) to prevent cable capacitance from loading the source.
Clean board surface: Solder flux residue, moisture, and other contaminants lower surface resistivity. Clean the board thoroughly after soldering, or use a conformal coating.
Guard ring: As mentioned earlier, surround the input pin with a ring connected to a low-impedance node at the same potential. For a buffer, the output (or non-inverting input) can drive the guard.
Avoid ground planes beneath the input: Stray capacitance to ground reduces input impedance at high frequencies. Remove the ground plane under the input pin and trace.
Use via stitching thoughtfully: Do not route high-impedance signals near vias that connect to noisy power planes.

Simulating the Buffer Circuit

Before building a prototype, simulate the buffer using SPICE (e.g., LTspice, PSpice, or QUCS). The simulation should include:

The op amp macro model from the manufacturer.
The source impedance (real and reactive).
Expected load impedance (including cable capacitance).
Power supply decoupling networks.
Any input protection resistors.

Simulation helps verify stability by examining the phase margin of the loop gain. It also reveals the impact of parasitic capacitance from layout (add a few pF from the input to ground to model stray capacitance). Adjust compensation components (Riso, feedback cap) until the circuit has at least 45° of phase margin for unity gain.

Applications of High-Input Impedance Buffers

These buffers are ubiquitous in precision analog systems. Notable examples include:

Biomedical Sensors

Electrocardiogram (ECG) and electroencephalogram (EEG) electrodes have high source impedance (typically 1–100 MΩ). A buffer placed directly at the electrode site prevents signal attenuation and reduces interference from cable motion artifacts. Specialized op amps like the AD8220 or INA118 are often used, but a simple buffer with low bias current works as a first stage.

Photodetector Front-Ends

Photodiode amplifiers often require a transimpedance configuration, but if the photodiode is used in photovoltaic mode (zero bias), its output impedance is very high. A buffer can be used to read the open-circuit voltage without loading the diode. Similarly, photomultiplier tubes and microchannel plates produce high-impedance current pulses that benefit from a buffer before further amplification.

Piezoelectric Sensors

Accelerometers and pressure sensors based on piezoelectric materials generate charge in response to mechanical stress. The equivalent source impedance is extremely high (10¹⁰–10¹² Ω). A buffer with <100 fA bias current and ultra-low input capacitance (e.g., OPA128) is required to avoid discharging the sensor. Such buffers are often housed in hermetic packages to minimize humidity leakage.

Chemical and pH Electrodes

Glass pH electrodes have a resistance of 10–1000 MΩ at room temperature. A high-impedance buffer (input current < 1 pA) is needed to read the pH voltage accurately. CMOS op amps such as the LMC6042 or LMC6062 are popular choices. Guard rings are mandatory on the PCB to reduce leakage.

Audio and Instrumentation

In high-end audio, buffer circuits are used at the output of passive preamplifiers or guitar pickups to preserve tonal quality. Instrumentation amplifiers often incorporate a high-impedance buffer at the input to maintain high common-mode rejection.

Testing and Verification

After assembly, verify the buffer's performance:

DC offset: Measure the output voltage with the input shorted to ground (or mid-supply). The offset should be within the op amp's datasheet specification (e.g., <1 mV).
Input impedance: Inject a known AC signal through a large series resistor (e.g., 10 MΩ) and measure the attenuation. For a perfect buffer, the gain remains 1. Any drop indicates finite input impedance.
Noise: Use a spectrum analyzer or oscilloscope with FFT to observe the output noise floor. Compare with calculated values.
Step response: Apply a fast square wave (≤1 kHz) with a low-impedance source and observe overshoot or ringing. Tweak compensation if needed.

Common Pitfalls and How to Avoid Them

Ignoring input capacitance: The op amp's input capacitance (common-mode and differential) plus stray PCB capacitance forms a capacitive divider with the source impedance, attenuating high-frequency signals. Choose an op amp with low input capacitance (e.g., <5 pF) and keep traces short.
Using inappropriate power supply voltages: Some sensors require the buffer to operate at signal levels near the supply rails. Select an op amp with rail-to-rail input and output if needed. Otherwise, ensure the input common-mode range includes the expected signal.
Forgetting electrostatic discharge (ESD) protection: High-impedance inputs are vulnerable to ESD. Add a series resistor (1–10 kΩ) and external TVS diodes or Zener clamps to within the supply rails. Ensure the added capacitance does not degrade bandwidth.
Relying on single supply without biasing: For single-supply operation, the input may need to be biased to a mid-rail voltage (e.g., using a resistive divider and a second buffer). Ensure the bias network presents a low impedance to the op amp's non-inverting input to avoid noise pickup.

Conclusion

Designing a high-input impedance buffer circuit with an op amp is a straightforward task when the correct device is selected and layout is executed with care. The key is to match the op amp’s input bias current, noise, and bandwidth to the source impedance and signal frequencies. By following the design principles, simulation steps, and practical tips outlined here, engineers can reliably build buffers that preserve the fidelity of sensitive signals across applications ranging from biomedical monitoring to high-precision sensor interfaces.

For further reading, consult the application notes from op amp manufacturers: Analog Devices AN-240: High Impedance Buffer Design and TI SBOA003: Op Amp Input Impedance and Bias Current. These resources provide deeper insight into the nuances of bias current cancellation and guard ring implementation.