Understanding IIR Filters in Embedded Systems

Infinite Impulse Response (IIR) filters are a fundamental building block in embedded signal processing. Their recursive structure—where the current output depends on both past inputs and past outputs—enables steep roll-offs and high stopband attenuation with far fewer coefficients than a Finite Impulse Response (FIR) filter of comparable performance. This efficiency is critical in low-power embedded devices where every CPU cycle and memory byte must be conserved. However, the same recursion that gives IIR filters their economy also introduces sensitivity to coefficient quantization, potential instability, and phase distortion. For battery-powered sensors, wearable health monitors, or industrial IoT nodes, the choice and optimization of IIR coefficients directly impact battery life, real-time performance, and signal fidelity.

Challenges in Coefficient Optimization

Optimizing IIR coefficients for low-power operation is a multi-objective problem. The primary challenges include:

  • Numerical Precision vs. Power: High-precision floating-point coefficients demand more power-hungry arithmetic units and larger memory footprints. In contrast, low-precision fixed-point coefficients can be processed on simpler, lower-power hardware but introduce quantization error that may alter filter response or cause instability.
  • Stability Margins: IIR filters must have poles inside the unit circle. Coefficient quantization can shift poles outward, moving the filter toward instability. Ensuring robust stability while minimizing coefficient word length is a tightrope walk.
  • Memory and Throughput Constraints: On resource-constrained microcontrollers (e.g., Cortex-M0, PIC, MSP430), each multiplication and addition contributes to energy draw. Coefficient scaling and algorithm structure must minimize both the number of operations and the data memory required for state variables.
  • Application-Specific Requirements: Medical devices demand very low noise and drift, while motor control loops need fast settling with limited overshoot. The optimization must respect these domain-specific constraints without overshooting power budgets.

Techniques for Coefficient Optimization

Developers can employ several techniques to reduce power consumption while preserving acceptable filter characteristics. Each technique involves trade-offs and should be validated with simulation and on-target testing.

Quantization and Word-Length Reduction

Quantization is the reduction of coefficient precision from, say, double‑precision floating-point to 16‑bit or 8‑bit fixed-point numbers. The key considerations are:

  • Round-off Noise: Quantizing coefficients changes the filter’s pole-zero locations. A direct-form II implementation is especially sensitive to coefficient quantization for high-order filters. Biquad cascade (second-order sections) reduces sensitivity because each section’s coefficients are smaller and more manageable.
  • Bit-Width Selection: Sub-micron microcontrollers often have hardware multipliers that operate on 16‑bit or 32‑bit integers. Choosing a coefficient word length that matches the hardware multiplier width avoids software emulation overhead. For example, on a 32‑bit ARM Cortex-M4, using Q31 format for coefficients and states keeps all arithmetic in single-cycle multiply-accumulate instructions.
  • Static vs. Dynamic Scaling: Static coefficient scaling (e.g., multiplying all coefficients by a power of two before quantization) makes implementation efficient. Dynamic scaling adjusts signals at runtime to prevent overflow, but adds overhead that may negate power savings.

Coefficient Scaling and Normalization

Scaling can be applied either to the coefficients themselves or to the filter’s state variables to improve numerical conditioning and reduce quantization effects. Common approaches include:

  • Gain Compensation: Cascade stage gains are adjusted so that intermediate signals remain within a desired amplitude range, minimizing overflow and saturation. Lower amplitudes at intermediate nodes reduce switching activity in the arithmetic logic.
  • Normalization to Unit Circle: Rescaling the filter’s transfer function so that the maximum gain of any biquad section is unity. This prevents internal overflow and allows the use of smaller state variable word lengths.
  • Binary Scaling: Using powers-of-two for coefficients (e.g., shifting instead of multiplying) eliminates multiplier usage entirely for some taps. Although feasible only in special cases (e.g., certain notch filters), it yields dramatic power reduction.

Pruning and Coefficient Truncation

In many IIR implementations, some coefficients are negligibly small (e.g., below –60 dB of the main coefficient). Pruning eliminates these coefficients, replacing them with zero. This simplifies the filter structure and reduces the number of multiply-accumulate operations per sample. However, pruning must be applied carefully:

  • Effect on Frequency Response: Removing small feedforward coefficients mainly affects high-frequency stopband performance; removing small feedback coefficients can shift pole locations and compromise stability.
  • Adaptive Pruning: For time-varying systems, coefficients can be dynamically evaluated and pruned based on their magnitude relative to a threshold. The overhead of evaluation must be weighed against the savings.

Fixed-Point Arithmetic and Implementation

Replacing floating-point arithmetic with fixed-point is one of the most effective ways to cut power. Fixed-point operations use simple integer adders and multipliers, which are smaller and consume less dynamic power than floating-point units. Best practices include:

  • Word Length Selection: Determine the required coefficient precision through simulation of the worst-case response error. For many low‑pass and band‑pass filters, 12‑ to 16‑bit coefficients are sufficient. Increasing to 20‑ or 24‑bit yields diminishing returns in accuracy but linearly increases memory and logic power.
  • Overflow Management: Use saturation arithmetic or wrap-around depending on the application. Saturation prevents instability in the feedback path at the cost of a few extra cycles; wrap-around is simpler but may cause large transients.
  • State Variable Scaling: Scale state variables so that their average magnitudes are close to the midpoint of the numeric range. This reduces the probability of overflow and lowers the number of corrective shifts.

Algorithmic Optimization: Cascade and Lattice Forms

The choice of filter topology dramatically affects both coefficient sensitivity and computational cost:

  • Cascade (Biquad) Form: Breaking a high-order filter into second-order sections (biquads) reduces coefficient sensitivity and simplifies stability checking. Each biquad can be implemented with 5 coefficients (two feedback, three feedforward) and 2 state variables. This form is the de facto standard for low-power embedded implementations.
  • Lattice/Ladder Structures: Lattice IIR filters offer lower coefficient sensitivity than direct forms, especially for high-order or narrowband filters. They require twice the number of multiplications per section but can tolerate much coarser coefficient quantization. For ultra-low-power devices with small bit-width multipliers, lattice forms may be more energy-efficient overall.
  • Wave Digital Filters: These structures are derived from analog prototypes and maintain stability under parameter variations. They are more complex but are used in safety-critical audio or control systems where coefficient uncertainty is high.

Practical Implementation Tips

Simulation-Driven Coefficient Selection

Before writing any firmware, simulate the filter with quantized coefficients using a tool like MATLAB’s Filter Design Toolbox or SciPy. Evaluate the worst-case passband ripple, stopband attenuation, and phase distortion under all possible coefficient bit widths. Use statistical quantization (e.g., rounding) rather than truncation to preserve mean frequency response.

Hardware-Aware Implementation

Take advantage of hardware features available on the target MCU:

  • Hardware Multipliers and MAC Units: Use the MAC instruction to combine multiplication and accumulation in a single cycle. Avoid C libraries that implement multiplication in software.
  • DMA Transfers for Sample I/O: Offload ADC and DAC operations from the CPU so that the filter computation runs only when data is ready.
  • Low‑Power Sleep Modes: Structure the filter routine to execute quickly and return to sleep. Use interrupt‑driven or timer‑based sampling to minimize active time.
  • Single‑Cycle Barrel Shifters: For coefficient scaling that involves shifting, use the barrel shifter instead of a loop or separate shift instruction.

Testing and Validation

After implementing quantized coefficients, validate the filter on actual hardware under worst-case conditions:

  • Frequency Response Measurement: Sweep a sinusoidal input and measure output amplitude with a spectrum analyzer or oscilloscope. Compare to the ideal floating-point response.
  • Transient Response: Apply a step input and observe settling time, overshoot, and ringing. Instability due to coefficient quantization often manifests as oscillation or slow divergence.
  • Power Measurement: Use a shunt resistor or a dedicated power profiler (e.g., Joulescope, Otii) to measure the current consumption of the filter routine in isolation. Compare fixed-point vs. floating-point implementations.

Leveraging Existing Libraries

Do not reinvent the wheel—many vendors provide optimized filter libraries for their parts:

  • ARM CMSIS-DSP offers a complete set of fixed-point (q15, q31) and floating-point (f32, f64) IIR filter functions. They are hand-tuned for Cortex-M CPUs and include biquad cascade and direct forms.
  • TI TMS320C2000 Control Library includes optimized IIR functions for the C28x and CLA co-processors. These are designed for real-time motor control with fast cycle times.
  • Microchip MPLAB Harmony provides filter blocks for PIC32 and SAM MCUs, with pre‑configured coefficients for common low‑pass and high‑pass types.

Case Study: 4th‑Order Low‑Pass IIR on a Cortex-M0+

Consider a heart‑rate monitor that needs a 4th‑order Butterworth low‑pass filter with a cutoff frequency of 5 Hz and a sampling rate of 200 Hz. Using direct‑form II with 32‑bit floating-point coefficients, the filter consumes 5.2 µA at 48 MHz (active). By converting to biquad cascade with 16‑bit fixed-point coefficients, the current drops to 2.1 µA—a 60% reduction—while still meeting the <3 dB passband ripple requirement. The biquad structure also ensures that quantization does not push poles outside the unit circle. An additional 5% gain can be achieved by pruning two negligible feedforward coefficients (below −60 dB).

Conclusion

Optimizing IIR filter coefficients for low-power embedded devices requires a systematic approach that balances numerical accuracy, computational load, and hardware constraints. Quantization, scaling, pruning, and algorithmic restructuring, when applied judiciously, can cut energy consumption by more than half without sacrificing signal quality. The key is to select the right topology (e.g., biquad cascade or lattice), match coefficient word length to the MCU’s arithmetic unit, and thoroughly test the quantized filter under real-world conditions. By following the techniques outlined here, developers can deploy efficient, reliable IIR filters that extend battery life and meet stringent performance targets.