Foundations of Wireless Power Transfer and the Role of PCB Layout

Wireless charging systems, particularly those based on inductive power transfer (IPT), have become ubiquitous in consumer electronics, medical devices, and industrial applications. The promise of eliminating physical connectors and enabling sealed enclosures places heavy demands on the power transfer efficiency, electromagnetic compliance, and thermal performance of the system. While coil design and resonant tank tuning are often the focus of optimization, the printed circuit board layout underpins every aspect of system behavior. A suboptimal layout can introduce parasitic resistances, inductances, and capacitances that degrade efficiency, increase electromagnetic interference (EMI), and compromise safety certifications.

This article presents a comprehensive set of strategies for PCB layout optimization in wireless charging systems. The guidance applies to both the transmitter (Tx) and receiver (Rx) boards, covering initial coil integration, high‑current routing, grounding and shielding, resonant component placement, and validation techniques. Each recommendation is grounded in electromagnetic theory and practical hardware experience, aiming to help engineers achieve reliable designs that meet efficiency targets and regulatory limits.

Wireless power transfer in the near field relies on mutual inductive coupling between a primary (Tx) coil and a secondary (Rx) coil. An alternating current in the Tx coil generates a magnetic flux, a portion of which links the Rx coil and induces a voltage. The power transfer efficiency (PTE) is a function of the coupling coefficient k (determined by coil geometry, alignment, and distance) and the quality factors (Q) of both resonant circuits. PCB layout influences these parameters through parasitic elements that shift resonance frequencies, add ohmic losses, and create unintended coupling paths.

Resonant versus non‑resonant topologies further affect layout sensitivity. Most modern systems use series‑series or series‑parallel resonant compensation to achieve higher efficiency and looser alignment tolerance. The passive components (capacitors, inductors) and their PCB interconnects must be placed to minimize stray inductance and resistance in the resonant loop. For wireless power transfer in the 100–205 kHz range (e.g., the Qi standard), skin effect and proximity effect losses become significant in thick copper traces; at higher frequencies such as 6.78 MHz (AirFuel standard), dielectric losses and parasitic inter‑winding capacitance dominate.

Coil Integration and Trace Optimization on the PCB

Coil Geometry and Copper Thickness

The Tx and Rx coils are often implemented as spiral traces on the PCB to reduce assembly cost and height. Critical layout parameters include:

  • Trace width and spacing: Wider traces reduce DC resistance and improve current handling, but increase eddy current losses in nearby conductive planes. A typical guideline is to use copper thickness of at least 2 oz (70 µm) for high‑current Tx coils; 4 oz copper is recommended for applications beyond 15 W. The spacing between turns should be at least twice the copper thickness to minimize turn‑to‑turn capacitance.
  • Number of turns and inner diameter: The inductance of a PCB coil is proportional to the square of the number of turns and the mean radius of the spiral. During layout, ensure that the inner diameter is large enough to accommodate the shield or ferrite sheet that will be placed behind the coil. A tightly wound coil with many turns may have excessive self‑capacitance, reducing the self‑resonant frequency (SRF).
  • Coil placement relative to the PCB edge: Keep the coil at least 10 mm away from board edges and from any large copper pours that are not part of the coil structure. This reduces fringe field losses and prevents unintentional coupling to ground planes.

For receivers, the coil is typically placed on the bottom layer of the PCB (closest to the transmitter) with a ferrite shield on the opposite side. The shield protects the system metal (battery, chassis) from eddy current heating and concentrates the magnetic field. Ensure that the shield is electrically conductive only in the vertical direction—use multi‑layer ferrite sheets or pattern the copper pour to avoid shorting the magnetic flux.

High‑Current Return Paths and Loop Area

The power stage of the transmitter consists of a full‑bridge or half‑bridge inverter that drives the resonant tank. The commutation loop formed by the MOSFETs, DC link capacitor, and the tank input must have the lowest possible stray inductance. A 10 mm² current loop can add 5–10 nH of parasitic inductance, which at 200 kHz results in a reactive impedance of 6–13 mΩ—negligible, but at 6.78 MHz it rises to 213–425 mΩ, significantly altering the resonant frequency and causing voltage overshoots across the FETs.

Use the following layout practices for the power inverter:

  • Place the DC‑link ceramic capacitors physically as close as possible to the high‑side and low‑side MOSFET drain/source pins. For best performance, use a low‑volume “cake” stack of multiple 1206 or 0805 capacitors directly underneath the FETs.
  • Route the tank coil connections using paired traces (or coplanar waveguide) to minimize the loop area. Avoid running the coil traces on separate layers without a guard trace or ground plane below—this increases loop inductance and couples noise to the board.
  • Use multiple vias for high‑current transitions between layers. A single via of 0.3 mm diameter adds ~1 nH; paralleling vias reduces both inductance and resistance.

Grounding Strategies and Shielding Techniques

Solid Ground Plane under the Coil Area: Yes or No?

A common dilemma is whether to place a solid ground plane directly under the Tx or Rx coil. At lower frequencies (< 1 MHz), a ground plane under the coil acts as a shorted turn: it heavily dampens the magnetic field, reduces k, and induces eddy currents that cause losses and heating. Therefore, always remove copper pours and ground planes from the area directly underlying the coil. The keep‑out zone should extend at least to the outer diameter of the coil plus 3–5 mm.

For the rest of the board, a solid ground plane is beneficial to control EMI and provide a low‑impedance return path for control and communication signals. To connect the ground plane to the chassis or shield enclosure, use multiple ground vias around the perimeter of the board, but avoid creating loops that intersect the coil’s magnetic field.

Shielding the Receiver from the Battery and Metallic Components

In a wireless charging receiver, the coil is often mounted on the same PCB that carries the battery connector and other high‑current circuits. Without proper shielding, eddy currents induced in the battery leads or in the shield can of the battery pack will heat those components and reduce efficiency. The standard solution is a ferrite sheet (e.g., a sintered ferrite tile or a flexible ferrite polymer) placed between the coil and the metallic structures. In the PCB layout, provide a soldering pad for the shield so that it can be electrically connected to the receiver ground via a low‑impedance path. This connection drains any induced common‑mode currents back to the source.

For the transmitter, a similar ferrite shield on the bottom of the PCB (opposite side from the coil) minimizes coupling to metal in the device enclosure (e.g., a metal desk surface). The shield should be conductive only for AC currents below the operating frequency, which is why ferrite is used rather than a solid copper plane.

Component Placement for Resonant Tank Tuning

The resonant capacitors (Cp and Cs in series‑series compensation) must be placed with extreme care to maintain the desired resonant frequency. Even a few pF of parasitic capacitance added to the tank can shift the operating point by several kilohertz at 6.78 MHz.

  • Place capacitors immediately adjacent to the coil pads. The trace length between the capacitor terminal and the coil terminal should be less than 5 mm. This ensures that the stray inductance in that loop is negligible.
  • Use multiple parallel capacitors to reduce ESR and ESL. For example, two 10 nF C0G capacitors in parallel have half the ESL of a single 22 nF capacitor, and they distribute the current evenly. This reduces voltage stress and improves reliability.
  • Avoid running high‑speed digital traces or clock lines near the resonant tank components. The magnetic field from the coil can couple noise into these signals, and conversely, digital noise can propagate into the power path via parasitic capacitive coupling. Maintain a distance of at least 2 mm from the tank components to any sensitive circuitry.
  • For the receiver side, consider integrating the resonant capacitor inside the ferrite shield stack to minimize the loop formed by the capacitor and the coil. This loop can radiate noise if not kept small.

Thermal Management in the Power Stage

Heating in wireless power systems originates primarily from coil copper losses, core losses in ferrite shields, and conduction losses in the inverter MOSFETs. The PCB layout must support heat dissipation without degrading performance.

  1. Copper efficiency: Use wider traces than minimum current rating would indicate—a 3 oz copper trace 5 mm wide can handle 5 A with less than 20°C rise. For the Tx coil, consider using a filled spiral with copper thickness built up via multiple solder masks (e.g., coin technology) to reduce DC resistance.
  2. Via stitching for heat spreading: Under the inverter MOSFETs and the coil pads, stitch multiple thermal vias (0.3 mm diameter, 0.5 mm pitch) to a ground plane or a dedicated heat‑spreader copper pour on the opposite side. The vias should be fully filled or tented to prevent solder wicking during assembly.
  3. Ferrite shield cooling: Ferrite materials have low thermal conductivity. In high‑power systems (> 15 W), provide a copper island on the layer opposite the ferrite that is connected through thermal vias to the PCB outer layer. This island can be coupled to a heatsink or the chassis.

EMI Mitigation: Filtering and Layout Techniques

Wireless charging transmitters are inherently EM noise sources—the rapid switching edges of the inverter excite harmonics that can peak in the FM band and above. The PCB layout can reduce conducted and radiated emissions through several proven methods:

  • Integrated LC filter at the power input. Place a series ferrite bead followed by a 100–470 nF ceramic capacitor right at the input connector. The ferrite bead should handle the full DC current without saturating—select one with < 5 mΩ DCR.
  • RC snubbers across the inverter output. Even a small snubber (e.g., 1 nF + 2.2 Ω) across the tank input can damp high‑frequency ringing without affecting the fundamental resonance. Place the snubber components as close as physically possible to the FET drain‑source terminals.
  • Spread‑spectrum clocking, though not strictly a layout technique, can be enabled by layout that keeps the spread‑spectrum oscillator away from the coil magnetic field. Provide a guard trace around the oscillator if it must reside on the same board.
  • Split the ground plane between the digital control section and the power section. Use a single‑point star‑ground connection at the DC input bulk capacitor. This prevents switching noise from contaminating the communication channel (e.g., Qi modulation) that rides on the same coil.

Testing and Validation: From Simulation to Production

No PCB layout is final without verification. The following tests should be performed at the prototype stage, and the results fed back into the layout for revision if necessary.

Network Analyzer Measurements

Use a vector network analyzer (VNA) to measure the two‑port S‑parameters of the coupled coils. The S21 transmission peak gives the coupling coefficient and the resonant frequency. If the measured resonance is more than 5 % off from the design target, adjust the capacitor values or re‑examine parasitic inductances in the tank loop. A VNA can also identify unintended resonances caused by parasitic coupling between the coil and other board traces.

Power Transfer Efficiency (PTE) Test

Measure input DC power to the transmitter and output DC power from the receiver rectifier. Efficiency mapping at various alignments reveals the sensitivity of the layout to misalignment. A drop of more than 10 % efficiency at 2 mm offset often indicates poor magnetic design or excessive eddy current losses in nearby copper pours—verify the keep‑out zones on the layout.

Thermal Imaging

During full‑power operation, use a thermal camera to identify hot spots. Hot areas outside the coil (e.g., on the ground plane edge) signal induced eddy currents. Modify the layout by widening the keep‑out zone or adding slots in the ground plane to interrupt the loop path.

EMI Compliance Scan

Radiated emissions from the coil and the power loop dominate. A near‑field probe coupled with a spectrum analyzer can locate emission hot spots. If the board fails CISPR 22 or FCC Part 15, consider adding a ferrite shield or a copper shield enclosure (connected to ground) over the transmitter electronics.

Additional Resources and Best Practices

For engineers diving deeper into wireless power PCB layout, the following references provide authoritative guidance:

  1. Texas Instruments “AN‑2011 – Layout Guidelines for Wireless Power Transmitters Using the bq500410A” – practical recommendations for coil interface and snubber placement.
  2. Würth Elektronik “Trilogy of Magnetics – Design Guide for EMI and EMC” – covers ferrite selection and shielding for inductive links.
  3. Qi 1.2.4 and 2.0 Communication Protocol Specification – contains guidelines for antenna (coil) design and minimum layout requirements for interoperability.

In addition, consider using PCB simulation tools such as ANSYS Q3D or FastHenry to extract parasitic inductances and capacitances from the layout before prototyping. A 15‑minute simulation can save two weeks of respin cycles.

Summary of Actionable Layout Rules

  • Keep copper away from the coil area — both ground planes and signal traces. Use a keep‑out zone of at least coil outer diameter + 3 mm.
  • Minimize area of the power loop — pair high‑side and low‑side components, place DC link caps directly across the inverter.
  • Use thick copper (2 oz minimum) for coil and power traces — 4 oz if space permits and power exceeds 15 W.
  • Place resonant capacitors within 5 mm of coil pads — parallel multiple capacitors to reduce ESL.
  • Integrate ferrite shields on both Tx and Rx — connect them to ground with > 10 thermal/vias.
  • Snub the inverter output — RC snubber across tank input to damp ringing.
  • Test early and iterate — VNA and thermal imaging are indispensable tools for final layout tuning.

By applying these strategies systematically, engineers can achieve wireless power designs that deliver high efficiency, robust immunity to alignment variations, and compliance with international EMI standards. The PCB layout is not merely an afterthought to the magnetic design—it is the medium through which the magnetic link is formed, stabilized, and protected from its own environment.