Understanding Power Supply Rejection Ratio in Precision Acquisition

Power Supply Rejection Ratio (PSRR) is a critical specification that quantifies how well a component rejects fluctuations on its supply pins from reaching the output. It is defined as the ratio of supply voltage change to resulting output change, expressed in decibels: PSRR (dB) = 20 log₁₀ (ΔVsupply / ΔVout). Higher numbers indicate stronger attenuation. For example, an op-amp with 100 dB PSRR at DC would turn a 1 V ripple on the supply into only 10 µV at the output under ideal conditions. However, PSRR is not constant across frequency; it typically begins to roll off after a few hundred hertz, dropping at 20 dB per decade or faster. This means that high-frequency noise from switching regulators, digital clocks, or RF transmitters can couple into the signal path even when the DC specification looks stellar.

In systems with dual supplies (such as ±15 V), positive and negative rails often have different rejection (PSRR+ and PSRR−) due to asymmetrical internal circuit topologies. For single-supply parts, the specified PSRR usually applies to the positive rail. Data sheet graphs also condition measurements on load current, common-mode voltage, and temperature—ignoring these conditions can lead to over-optimistic performance estimates. Understanding the frequency-dependent nature of PSRR is essential for designing robust precision data acquisition systems.

Why PSRR Matters for High-Resolution Data Acquisition

Precision systems targeting 16 bits or more, with noise floors below 1 µVRMS, are especially vulnerable to power-supply noise. Supply disturbances couple into the analog signal path, creating offset drift, gain errors, and random noise that degrade the effective number of bits (ENOB) of the ADC. Even when the ADC itself has good PSRR, surrounding circuitry—amplifiers, references, filters—may not. For instance, supply noise injected into a precision amplifier modulates its input offset voltage, producing an error that is indistinguishable from the actual sensor signal. This directly increases measurement uncertainty and shrinks dynamic range.

In real-world applications, the impact is tangible: industrial weigh scales suffer drift from 50/60 Hz mains ripple; medical ECG systems can have subtle diagnostic features hidden by switching regulator noise. Therefore, the overall system PSRR—accumulated across every active device from reference to ADC driver—must be analyzed quantitatively, not just as a single data sheet number. A system may have components with individual PSRR over 100 dB, yet the combined effect can be much worse due to layout and interaction.

PSRR in the Data Acquisition Signal Chain

Operational Amplifiers and Instrumentation Amplifiers

The analog front-end processes the smallest signals and is the most vulnerable to power-supply noise. Precision op-amps often claim DC PSRR above 120 dB, but at 100 kHz that figure can drop below 60 dB. For an amplifier set to a gain of 100, a 10 mVRMS supply ripple at 100 kHz could produce an output error of several millivolts if PSRR is poor. Instrumentation amplifiers (in-amps) rely on tightly matched internal resistors, making them especially sensitive to common-mode supply noise: any imbalance between PSRR on positive and negative rails converts common-mode noise into a differential error that gets amplified directly.

Chopper-stabilized and auto-zero amplifiers achieve excellent DC PSRR and low offset drift, but designers must verify that the chopping frequency does not introduce supply-dependent artifacts at the output. High-frequency supply noise can alias with the chopping clock, producing in-band spurs. Data sheets from Texas Instruments and Analog Devices include detailed PSRR-versus-frequency curves that should be consulted for every amplifier in the signal path.

Analog-to-Digital Converters (ADCs)

Precision ADCs, especially delta-sigma architectures, incorporate on-chip references, clock generation, and digital filtering. The power supply biases both analog buffers and the digital core. Any ripple can inject charge into the switched-capacitor sampling network, causing gain and offset variations. Many precision ADCs specify DC PSRR above 90 dB, but supply-coupled noise can also produce intermodulation products that fold into the passband through the digital filter's stopband. The Analog Devices guide to measuring PSRR discusses these effects thoroughly.

When the ADC includes a programmable gain amplifier (PGA), that stage’s PSRR becomes dominant. Rejection often degrades as gain increases because the supply noise is also amplified by the PGA. In multiplexed systems, PSRR can vary with input impedance, so characterization across the full operating range is necessary. Modern ADCs sometimes offer internal supply monitoring or test modes to help assess PSRR in situ.

Voltage References

A voltage reference is often assumed to be a quiet source, but its output is modulated by supply variations. The reference's PSRR determines how much ripple translates into a gain error for the ADC. In ratiometric systems where the same reference drives both sensor excitation and ADC, poor PSRR induces a systematic error that tracks supply noise. For absolute measurements, a reference with high PSRR over the full bandwidth of interest is essential. Buried-zener references offer excellent low-frequency PSRR, while bandgap references may have limited high-frequency rejection without external filtering.

Practical designs often place an RC low-pass filter after a precision reference to improve high-frequency PSRR. Care must be taken to avoid voltage drop across the series resistor and to ensure the filter's output impedance does not interact with the ADC’s dynamic current demand. Low-ESR ceramic capacitors directly at the reference output help maintain low impedance over a wide frequency range.

Linear and Switching Regulators

The power supply itself is often the source of noise. Linear regulators produce low-frequency ripple at mains harmonics and wideband thermal noise; their PSRR is high at low frequencies but falls off above a few kilohertz. Switching regulators generate ripple at the switching frequency (hundreds of kHz to MHz) plus high-frequency ringing and EMI. The regulator's own PSRR determines how much ripple passes to the load. Ultra-low-noise LDOs like the TPS7A49 achieve PSRR above 60 dB up to 10 MHz, making them suitable for sensitive analog circuits. However, even the best regulator cannot compensate for poor layout or inadequate decoupling.

Sources of Power-Supply Noise in Mixed-Signal Systems

To design for good PSRR, engineers must understand the noise profiles their supplies present. Linear regulators contribute low-frequency ripple, while switching regulators produce switching-frequency ripple and broadband noise. Digital circuits—FPGAs, microcontrollers, high-speed interfaces—inject current spikes that create ground bounce and supply transients. These disturbances can propagate through power distribution networks, capacitive coupling, or radiated EMI. In mixed-signal PCBs, isolating these noise sources from the precision analog chain is the central challenge. The analog supply should be derived from a clean source, often a dedicated LDO fed from a filtered rail, with careful physical separation.

Measuring PSRR in a Real System

Characterizing PSRR on an actual PCB is more complex than reading a data sheet number. Board parasitics, decoupling networks, and shared ground impedances all affect the result. A common lab technique injects a small AC signal into the supply rail using a line injector or wideband transformer, then measures the resulting output disturbance with a spectrum analyzer or lock-in amplifier. The injection point must not alter supply impedance or inject common-mode currents. For ADCs, capture digital outputs and perform an FFT to identify spurs at the injected frequency, yielding accurate rejection in dB.

Engineers often find that effective board-level PSRR is 10–20 dB worse than the component specification. This degradation arises from inductance in power traces, inadequate ground planes, and substrate coupling. Thus, layout and decoupling are as important as component selection.

Design Strategies to Maximize Power-Supply Rejection

Component Selection with PSRR Curves

Choose active devices with inherently high PSRR across the required frequency range. Modern precision op-amps specify PSRR out to several hundred kHz; some integrate internal filtering to boost high-frequency rejection. Look for components with flat PSRR curves rather than deep notches that could align with switching noise. When examining data sheets, note the test conditions: PSRR is often specified at particular supply voltage and common-mode input voltage; applying the part under different conditions may yield different results.

Multi-Stage Power Supply Filtering

A robust decoupling strategy uses multiple stages. A typical chain: switching regulator → LC filter → LDO with high PSRR → point-of-load filtering with ferrite beads and capacitors. At each analog IC, combine bulk (10 µF to 47 µF) and high-frequency ceramic (0.1 µF to 1 µF) capacitors placed as close as possible to supply pins. Minimize series inductance from capacitor mounting and traces; otherwise the self-resonance frequency limits high-frequency performance.

For extremely sensitive nodes like voltage references and ADC power pins, a dedicated LDO with a noise-reduction pin can provide an extra 20–40 dB of rejection when an external capacitor is added. This technique is common in 24-bit weigh-scale systems. Verify the LDO's PSRR at the frequencies where the upstream regulator operates—many LDOs lose rejection above 100 kHz.

PCB Layout and Grounding

No amount of component PSRR can compensate for a poorly laid-out board. Use a solid ground plane with no cutouts under sensitive analog traces. Consider a star ground or a single connection point between analog and digital ground domains under the ADC. Route power as wide, low-inductance polygons. Keep analog and digital circuit areas physically separated; place voltage regulators close to their loads. Never run high-impedance analog signal traces parallel to noisy power or clock traces. A guard trace connected to ground can help isolate sensitive nodes. The Analog Devices grounding guide provides practical examples that directly affect PSRR.

Differential Signaling and Isolation

Galvanic isolation of the analog front-end from noisy digital processing can break conducted noise paths. Isolated DC-DC converters combined with digital isolators for SPI or I²C allow precision circuitry to operate from a clean isolated supply. Differential signaling at the input—using fully differential amplifiers driving differential ADC inputs—improves rejection of common-mode supply noise that couples into the inputs.

Case Study: Improving PSRR in a 24-Bit Sensor Interface

Consider a system measuring strain-gauge bridge outputs with 0.1 µV resolution. The signal chain: instrumentation amplifier (G=128), 24-bit delta-sigma ADC, 2.5 V reference. The system is powered from a single 5 V rail that also supplies a microcontroller and a Bluetooth module. Initial prototypes showed random noise spikes and DC offset drift of several microvolts during Bluetooth transmissions, even though the ADC and amplifier claimed PSRR above 100 dB.

Investigation revealed that the analog supply, from a simple 3.3 V LDO, had only 40 dB PSRR at 2.4 GHz due to RF energy coupling through the LDO's pass element and PCB traces. The fix involved three steps: first, replace the LDO with an ultra-low-noise LDO (TPS7A49) using an external noise-reduction capacitor for high PSRR up to 10 MHz. Second, insert a pi-filter (ferrite bead plus two capacitors) before the LDO to pre-attenuate high-frequency noise. Third, revise the layout: move analog section to a quiet corner, use a continuous ground plane, and add a guard ring around the input stage. After these changes, noise spikes disappeared and DC offset drift fell below 0.05 µV. Effective system PSRR from the 5 V rail at 2.4 GHz improved by over 30 dB—despite no component listing that frequency.

PSRR Testing in Production

Full frequency-sweep PSRR testing on every unit is impractical for high-volume manufacturing. Instead, design a pass-fail test by injecting a known noise frequency (often from the system’s own regulator or an external generator) and comparing the ADC's noise floor or a specific spur amplitude against a limit. Some precision ADCs include built-in self-test features that allow applying a test signal to an internal multiplexed channel, enabling the system to assess its own noise performance under different supply conditions. This can catch degrading PSRR due to component variations or assembly defects.

Maintaining PSRR Over Temperature and Lifetime

PSRR is not static. As semiconductors age and temperature varies, transistor transconductance and passive component impedances change. Ceramic capacitors lose capacitance under DC bias and at temperature extremes, shifting the corner frequency of decoupling networks and reducing high-frequency PSRR. Aluminum electrolytic capacitors can dry out, increasing ESR. Always derate capacitors and consider using X7R or C0G dielectrics for better stability. Verify PSRR performance at expected temperature extremes and after accelerated life testing for high-reliability systems such as aerospace or medical equipment.

Summary of Best Practices

  • Analyze PSRR curves over frequency rather than a single dB value; account for worst-case operating point.
  • Select components with flat PSRR responses; verify they are adequate at the switching frequencies present.
  • Implement multi-stage power-supply filtering with LDOs, ferrite beads, and carefully chosen capacitors.
  • Design a low-impedance, partitioned PCB with solid ground planes and separate analog/digital power domains.
  • Validate system PSRR by measurement under real load and layout conditions; laboratory tests prevent field failures.
  • Consider galvanic isolation when conductive filtering is insufficient.
  • Derate capacitors and test over temperature and life to ensure consistent PSRR throughout the product's lifetime.

Conclusion

Power Supply Rejection Ratio is far more than a single data sheet line; it is a dynamic, system-level parameter that fundamentally affects the accuracy of data-acquisition systems. By carefully analyzing the entire signal chain—from reference to amplifier to ADC—and treating the power supply as an integral part of the analog design, engineers can achieve the sub-microvolt noise floors that modern applications demand. A deep understanding of PSRR, combined with deliberate component selection, disciplined layout, and thorough validation, enables measurement systems that perform reliably even in the most electrically hostile environments.