The stability of control systems is fundamental to the safe and efficient operation of everything from industrial robots to autonomous vehicles. Two interrelated parameters that critically influence this stability are the controller sample rate and the computational delay. While often considered separately, their combined effect can make the difference between a well-damped response and catastrophic oscillation. This article provides an in-depth look at how sample rate and delay affect system stability, offering practical guidance for engineers designing real-time control systems.

Fundamentals of Sample Rate in Digital Control

In any digital control system, the controller reads sensor measurements, computes a control action, and outputs a command at discrete intervals. The frequency of these updates is the controller sample rate, typically expressed in Hertz (Hz) or as the sample time Ts (seconds per sample). The sample rate dictates how often the controller can react to changes in the process variable. A higher sample rate generally allows the controller to track faster dynamics and reject disturbances more effectively.

The Nyquist-Shannon Sampling Theorem

A fundamental constraint on sample rate comes from the Nyquist-Shannon sampling theorem: to accurately reconstruct a continuous signal, the sampling frequency must be at least twice the highest frequency component present in the signal. In control systems, this means the sample rate must be greater than twice the system's closed-loop bandwidth. Falling below this threshold leads to aliasing, where high-frequency signals masquerade as low-frequency disturbances, degrading stability and performance. Engineers typically set the sample rate 10 to 20 times higher than the desired closed-loop bandwidth to provide adequate margins.

For a deeper dive into the Nyquist criterion, refer to the Wikipedia article on the Nyquist–Shannon sampling theorem.

Computational Delay: Sources and Measurement

Computational delay, often called input-output latency or dead time, is the time elapsed from when a sensor measurement is sampled until the corresponding control output is applied. This delay arises from multiple sources:

  • Sensor acquisition and conversion delay: Time to digitize analog sensor signals (ADC conversion).
  • Communication latency: Delays over buses (CAN, Ethernet, SPI) or wireless links.
  • Processor computation time: Execution time for control algorithms, filtering, and logic.
  • Output conversion delay: Digital-to-analog (DAC) settling time or actuator driver delays.

Computational delay is often expressed as a fraction of the sample period Ts. In many real-time implementations, the total delay is assumed to be one sample period (or less), but in practice it can vary with processor load, interrupt handling, and scheduling jitter.

Effect on Phase Margin

Delay introduces a phase lag proportional to the frequency of the signal. For a simple time delay τ, the phase lag at frequency ω is φ = −ωτ radians. In a control loop, this additional phase lag reduces the phase margin, a key stability metric. A phase margin below 30 degrees often results in a poorly damped or oscillatory response. Because delay is multiplicative with frequency, even small delays can become destabilizing at high loop bandwidths.

The Interplay of Sample Rate and Delay on Stability

Sample rate and computational delay are not independent. Increasing the sample rate (reducing Ts) generally reduces the per-sample delay but may increase the computational load, potentially extending the total delay in absolute time. Conversely, lowering the sample rate reduces computational burden but increases the latency between measurements and control actions, hurting responsiveness.

From a discrete-time control perspective, the system's behavior is analyzed using the z-transform and root locus techniques. The closed-loop poles move with both sample time and delay. A rule of thumb is that the total loop delay should be less than about one-tenth of the dominant time constant for stability to be robust. In many textbooks, the allowable delay budget is expressed as a fraction of the sample period; overly aggressive sample rates can push delay beyond safe limits.

Phase-Lag Compensation and Filtering

Designers sometimes employ phase-lead compensation or Smith predictors to counteract the effects of delay. However, these methods have limitations. For example, a Smith predictor relies on an accurate plant model; modeling errors can cause instability. Anti-aliasing filters, while necessary, also introduce phase lag and must be accounted for in the delay budget.

Practical Design Guidelines and Trade-offs

Optimizing sample rate and delay is a multi-objective problem. The following table summarizes the trade-offs:

ParameterHigh ValueLow Value
Sample RateFaster response, better disturbance rejection, higher computational load, tighter delay budgetLower computational load, larger phase margin erosion per delay, increased quantization error
Computational DelayDegrades phase margin, limits achievable bandwidth, may require compensationBetter stability, allows higher sample rates, more expensive hardware

Selecting Sample Rate Based on System Dynamics

A systematic approach begins with identifying the system's natural frequency and desired closed-loop bandwidth. For second-order systems, the sample rate should be at least 10 times the undamped natural frequency. For systems with sensor noise, oversampling and decimation can improve resolution without increasing the control loop sample rate. Engineers must also consider the processor's ability to execute the control algorithm within the sample interval; this often dictates the upper bound on sample rate.

Minimizing Computational Delay

To reduce delay:

  • Use hardware with deterministic execution (e.g., field-programmable gate arrays, FPGAs, or real-time operating systems, RTOS).
  • Optimize code by reducing mathematical operations (e.g., fixed-point arithmetic, lookup tables).
  • Pipeline sensor acquisition with computation where possible.
  • Choose communication protocols with low latency (e.g., QSPI instead of I²C).

A practical resource on real-time scheduling is available from OSDev's Real-Time System page.

Case Studies in Stability Failure

Robotics: High-Bandwidth Torque Control

In collaborative robots, torque control loops often run at 1–10 kHz. A computational delay of 50 microseconds (0.05 ms) already introduces a 0.5° phase lag at 100 Hz, reducing phase margin by several degrees. If the processor is overloaded and the loop time varies, the resulting jitter can cause limit cycles or audible vibration. Designers must carefully profile worst-case execution times and add timing margins.

Aerospace: Flight Control Actuation

Flight control systems (fly-by-wire) require extremely deterministic timing. Sample rates of 400–800 Hz are common, and total loop delay must be under 2–3 milliseconds. A delay of just one extra millisecond due to a slow bus or heavy CPU load has led to pilot-induced oscillations (PIO) in some aircraft prototypes. Rigorous testing and hardware-in-the-loop simulation are mandatory.

For further reading on flight control stability margins, see NASA Technical Reports Server: Handling Qualities and Stability Margins.

Advanced Considerations: Variable Sample Rates and Multi-Rate Systems

Some modern controllers use variable sample rates to adapt processor load, but this introduces unpredictability. Multi-rate systems employ different sample rates for different control loops (e.g., fast inner current loop, slower outer position loop). The aliasing and delay interaction between rates must be carefully analyzed using multirate z-transform methods.

Jitter and Its Effect on Stability

Jitter—variation in the sample interval or delay—can be more damaging than a fixed delay because it introduces nonlinearities and can excite high-frequency modes. Real-time operating systems with preemptive scheduling can reduce jitter, but careful priority assignment and interrupt handling are critical. For hard real-time systems, using a hardware timer to trigger sampling eliminates software jitter.

Conclusion

The controller sample rate and computational delay are twin levers that engineers must balance to achieve stable, high-performance control. A higher sample rate improves responsiveness but tightens the delay budget and increases computational demand. Excess delay erodes phase margin, potentially leading to oscillations or instability. By understanding the Nyquist criterion, phase margin mechanics, and the practical constraints of hardware and software, designers can select appropriate sample rates, minimize delay through careful implementation, and validate stability using both simulation and experiment. Ultimately, a robust control system is one where sample rate, delay, and algorithm complexity are harmonized to meet the application's dynamic requirements.

For those seeking a more mathematical treatment, the IEEE Control Systems Society publishes papers on discrete-time delay systems; an example is "Stability Analysis of Sampled-Data Control Systems With Input Delay".