Understanding Vias in PCB Design

In modern high-speed circuit boards, the humble via—a simple plated hole that connects different copper layers—has become a critical element that can make or break signal integrity. As data rates push into the gigahertz range, every millimeter of the signal path must be carefully controlled. Vias introduce discontinuities that can cause reflections, loss, and electromagnetic interference (EMI) if not designed properly. This article explores the fundamentals of via design, its impact on high-speed performance, and best practices that engineers should adopt to ensure reliable operation.

Whether you are designing a server motherboard, a 5G base station, or a high-frequency RF module, understanding via behavior is essential. We will cover via types, parasitic effects, design parameters, simulation techniques, and advanced manufacturing methods that help mitigate issues. By the end, you will have a comprehensive view of why via design matters and how to optimize it.

What Are Vias and Why Do They Matter?

A via is a small hole drilled through a printed circuit board (PCB) and then plated with copper to form an electrical connection between two or more layers. In multi-layer boards, vias allow signals, power, and ground to travel vertically. Without vias, complex routing on densely packed boards would be impossible. However, every via introduces a change in the transmission line geometry, creating an impedance discontinuity that can degrade high-speed signals.

At low frequencies (below a few megahertz), the parasitic inductance and capacitance of a via are negligible. But as clock speeds and data rates increase into the hundreds of megahertz and beyond, these parasitic elements become dominant factors. A poorly designed via can cause signal reflections, increase jitter, and even radiate unwanted energy. Therefore, via design must be treated with the same rigor as trace routing and stack-up planning.

Types of Vias

Engineers have several via types to choose from, each with specific advantages and trade-offs:

  • Through-hole vias (also called plated through-holes) penetrate the entire board. They are the simplest and cheapest but introduce long stubs that resonate at high frequencies.
  • Blind vias connect an outer layer to one or more inner layers without going through the entire board. They reduce stub length and save space.
  • Buried vias connect two or more inner layers only, not reaching the outer layers. They are used in high-density interconnect (HDI) designs to maximise routing area.
  • Microvias are very small blind vias (typically less than 150 µm in diameter) formed by laser drilling. They are essential for HDI boards and high-speed designs because of their low parasitic capacitance and inductance.

Choosing the right via type depends on cost, density, frequency, and manufacturing capabilities. For extremely high-speed signals (e.g., 25 Gbps and above), microvias and properly designed buried vias are often necessary.

Signal Integrity Issues Caused by Vias

When a high-speed signal travels through a via, it encounters a sudden change in impedance. Even if the trace is perfectly matched to 50 ohms, the via itself may present a different impedance due to its geometry and the surrounding return path. This mismatch leads to reflections that degrade the signal quality. Additionally, the via barrel acts as a metallic stub that can resonate at certain frequencies, causing notches in the insertion loss.

The primary parasitic elements of a via are:

  • Capacitance (C_via) – Concentrated between the via barrel and the adjacent ground/power planes. High capacitance lowers impedance, causing signal degradation.
  • Inductance (L_via) – Arises from the loop area of the signal current path. High inductance increases impedance and causes ringing.
  • Resistance (R_via) – DC and AC resistance due to the copper plating and skin effect at high frequencies.

These parasitics form a low-pass filter, attenuating high-frequency components and increasing rise time. In multi-gigabit designs, even a single poorly optimized via can close the eye diagram completely.

Via Stub Resonance

A via stub is the unused portion of a through-hole via that extends past the signal layer to the bottom of the board. At frequencies where the stub length equals a quarter wavelength, the stub behaves as an open-circuit quarter-wave resonator and creates a notch in the frequency response. For example, a 300-mil stub resonates near 6 GHz. This can severely attenuate signals in the X-band or above. To avoid this, designers often use backdrilling to remove the stub, or they use blind/buried vias that eliminate stubs entirely.

Design Parameters for High-Speed Vias

Several geometrical parameters influence via performance. Optimising each one is critical:

Via Diameter and Pad Size

Smaller vias have lower parasitic capacitance and inductance, making them preferable for high speeds. However, the minimum via size is limited by the PCB manufacturer's capabilities and the drill aspect ratio (board thickness to via diameter). Typical high-speed vias range from 8 to 12 mils for through-hole and 4 to 6 mils for microvias. The pad (or land) on each layer must be large enough to ensure reliable connection, but an oversized pad adds capacitance. A common guideline is to keep the pad diameter about twice the via diameter.

Anti-Pad Clearance

The anti-pad is the clearance hole in the ground/power planes around the via. Its diameter controls the impedance of the via. A larger anti-pad reduces capacitance and increases impedance, but it also creates a larger return-path discontinuity. For best results, the anti-pad should be carefully matched to the via diameter and the stack-up materials. Many high-speed designs use a non-functional pad style where inner layers have no pad except those that are electrically connected, reducing parasitic capacitance.

Via Spacing and Pitch

When multiple vias are used (e.g., for differential pairs or power distribution), the spacing between them affects mutual inductance and capacitance. Too close, and coupling becomes excessive; too far, and the return path becomes discontinuous. For differential signals, vias should be placed symmetrically and with controlled inter-via distance to maintain odd-mode impedance.

Via-in-Pad (VIP)

In high-density designs, vias are placed directly in component pads to save space and reduce trace length. This technique, called via-in-pad, requires filling and planarization to avoid solder voids. Although it minimises routing inductance, it can create a stress point during reflow. Properly filled and planarized VIP is common in BGAs and QFNs for high-speed signals.

Simulation and Modeling of Vias

Relying solely on rules of thumb is not sufficient for designs above a few gigahertz. Full-wave electromagnetic simulation (e.g., using Ansys HFSS, CST, or Keysight ADS) is necessary to accurately model via behavior. Engineers extract S-parameters of the via structure and include them in channel simulations. Important parameters to extract include insertion loss (S21), return loss (S11), and differential-to-common mode conversion (Scd21).

Many PCB design tools (Altium Designer, Cadence Allegro, Mentor PADS) offer integrated via modeling capabilities. They allow designers to specify via geometry and stack-up and automatically compute impedance and parasitics. However, for the most accurate results, a 3D field solver should be used, especially for complex via arrays or transitions between different transmission line types (e.g., microstrip to stripline).

For more detailed guidance on via modeling, consider reading Altium's documentation on via modeling in high-speed design or a white paper from Cadence on high-speed via analysis.

Manufacturing Considerations for High-Speed Vias

Even the best simulation is useless if the PCB manufacturer cannot produce the vias within tolerances. Key manufacturing aspects include:

  • Aspect ratio: The ratio of board thickness to via diameter. Most fabs can handle up to 10:1 for through-hole vias; higher ratios require specialized processes.
  • Plating uniformity: Thin or uneven plating increases resistance and inductance. Specify copper thickness (1 oz or 0.5 oz) and monitor via resistance.
  • Backdrilling: This secondary drilling operation removes via stubs. It requires careful alignment and a minimum remaining copper thickness. Backdrilling can reduce insertion loss by several decibels at high frequencies.
  • Via filling and capping: For via-in-pad, non-conductive paste (e.g., epoxy) fills the via, then copper caps the top. This prevents solder wicking and provides a flat surface for component attachment.
  • Via tenting: Some designs cover vias with soldermask to prevent accidental shorts. However, tenting can trap chemicals and cause reliability issues; consult your fabricator.

Advanced Techniques: Coaxial Vias and Grounded Via Fences

For RF and millimeter-wave designs, coaxial vias are used to create a shielded vertical transmission line. A central signal via is surrounded by multiple ground vias placed in a ring, approximating a coaxial structure. This reduces radiation and provides a well-controlled impedance. Similarly, grounded via fences (rows of vias) are placed along the edge of PCBs or around sensitive RF sections to suppress parallel-plate waveguide modes and prevent EMI.

An IEEE article on high-speed via design provides additional insights into resonance suppression techniques.

Best Practices Summary

To achieve reliable high-speed performance via vias, follow these guidelines:

  • Minimize stub length: Use blind, buried vias, or backdrilling. Keep stubs under 10 mils for signals above 10 GHz.
  • Optimize via diameter: Use the smallest diameter that the PCB fabricator can reliably produce. For differential pairs, keep via diameters consistent.
  • Control impedance: Calculate via impedance using field solvers. Match it to the trace impedance as closely as possible.
  • Place reference vias near signal vias: For every signal via that changes layers, place a ground via adjacent to it to provide a short return path.
  • Use via arrays for power distribution: Multiple vias in parallel reduce inductance and current density.
  • Simulate, don't guess: Always extract via models and include them in channel simulations for any high-speed serial link above 5 Gbps.

Conclusion

Via design is no longer a secondary consideration in high-speed PCB design. As data rates continue to climb, the parasitic effects of vias—capacitance, inductance, stub resonance—directly impact the reliability of the entire system. By understanding the types of vias, their electrical behavior, and the geometric parameters that control performance, engineers can mitigate signal integrity issues and achieve robust designs. Combining careful layout with simulation and close collaboration with PCB fabricators ensures that vias become an asset rather than a liability. For further reading, consult industry resources such as the Altium high-speed via design blog or the Microwave Journal's articles on via modeling.