Introduction: Why Grain Size Matters in Polycrystalline Silicon

Polycrystalline silicon (polysilicon) is the workhorse of the modern photovoltaic and semiconductor industries. Its electrical conductivity directly determines the efficiency of solar cells, the switching speed of transistors, and the overall performance of integrated circuits. While the material’s purity and doping level are well-known factors, the grain size of the crystalline domains plays an equally critical role. Understanding how grain size influences charge transport is essential for engineers and materials scientists who design fabrication processes to maximize device performance. This article provides a deep dive into the relationship between grain size and electrical conductivity in polysilicon, covering the underlying physics, experimental evidence, manufacturing strategies, and real-world applications.

What Is Polycrystalline Silicon?

Polycrystalline silicon is a form of silicon that consists of many small, randomly oriented single-crystal regions called grains. These grains are separated by grain boundaries—thin transition zones where the crystal lattice orientation changes abruptly. Polysilicon is produced through various methods, including chemical vapor deposition (CVD), float-zone refinement, and casting of ingots. Its electrical properties differ significantly from those of single-crystal silicon due to the presence of these grain boundaries.

In photovoltaic applications, polysilicon is often used because it offers a favorable balance between cost and efficiency. Compared to monocrystalline silicon, polysilicon cells are slightly less efficient (typically 14-18% vs. 17-22%) but are cheaper to manufacture. The difference in performance is largely attributable to the grain structure.

Fundamentals of Electrical Conductivity in Semiconductors

Electrical conductivity (σ) in semiconductors is given by σ = q(nμn + pμp), where q is the elementary charge, n and p are electron and hole concentrations, and μn and μp are their respective mobilities. In doped polysilicon, the carrier concentration is controlled by intentional impurity addition, but the mobility is strongly influenced by structural defects. Grain boundaries act as scattering centers and trapping sites, reducing the effective mobility of charge carriers. Therefore, even with identical doping levels, a polysilicon sample with smaller grains will exhibit lower conductivity than one with larger grains.

Carrier Scattering Mechanisms

Several scattering mechanisms degrade mobility in polysilicon:

  • Phonon scattering—dominant at high temperatures, but grain boundary scattering often dominates at room temperature in fine-grained material.
  • Ionized impurity scattering—from dopant atoms, but grain boundary effects can overshadow this.
  • Grain boundary scattering—carriers are scattered by the potential barriers at grain boundaries, which are caused by trapped charges and lattice mismatch.
  • Defect scattering—dislocations and point defects within grains also contribute, but their density is generally lower than the density of grain boundaries.

How Grain Boundaries Affect Conductivity

A grain boundary is not simply a geometrical interface; it contains a high density of dangling bonds and structural defects that create deep-level trap states. These traps capture majority carriers, depleting the adjacent grain regions and forming electrostatic potential barriers. The model developed by Seto (1975) is the classic framework for understanding this. In Seto’s model, the grain boundary is treated as a thin region of high trap density. Carriers must thermionically emit over the potential barrier to move from one grain to the next. The resulting effective conductivity depends exponentially on the barrier height, which in turn depends on the grain size and trap density.

The Seto Model in a Nutshell

For n-type polysilicon, the barrier height φB is given by:

  • If the grain size L is greater than the depletion width, φB ∝ Nt² / (Nd L), where Nt is the trap density per unit area and Nd is the doping concentration.
  • If L is small enough that the grains are fully depleted, the barrier height saturates.

This model predicts that conductivity increases monotonically with grain size, especially in lightly doped material. Experimental measurements, such as those from Seto’s original paper, confirm this trend.

Effect of Grain Size on Carrier Mobility

Mobility is the average drift velocity per unit electric field. In polysilicon, effective mobility μeff can be an order of magnitude lower than in single-crystal silicon of the same doping. As grain size increases, μeff improves because:

  • There are fewer grain boundaries to cross, so carriers scatter less frequently.
  • The potential barriers are lower because the density of trapped charge per unit length decreases.
  • Larger grains allow more carriers to remain within the neutral region of the grain, where mobility is higher.

For example, typical values for polysilicon with 1 µm grains might show μeff around 30 cm²/Vs for electrons, whereas grains of 10 µm can boost mobility to 100 cm²/Vs or more (depending on doping). This directly translates to higher conductivity.

Impact of Doping Concentration

The effect of grain size is modulated by the doping level. At low doping (Nd < 10¹⁶ cm⁻³), grain boundaries dominate and conductivity is very sensitive to grain size. At high doping (Nd > 10¹⁹ cm⁻³), the barrier becomes narrow and carriers can tunnel through, reducing the relative importance of grain size. However, in intermediate doping regimes—commonly used in solar cell emitters and thin-film transistors—grain size remains a critical parameter.

Experimental Observations and Data

Numerous experimental studies have measured conductivity as a function of grain size. A landmark study by Kamins (1980) showed that for polysilicon films deposited via low-pressure CVD, resistivity decreased by three orders of magnitude as grain size increased from 0.1 µm to 10 µm. More recent work using advanced recrystallization techniques has produced polysilicon with grains exceeding 100 µm, achieving conductivities within a factor of two of single-crystal silicon.

Another important finding is the existence of an optimal grain size for certain applications. For example, in thin-film polycrystalline solar cells, grain sizes of 1-10 mm are often sought because they provide high conductivity without requiring extremely high-temperature processing that would degrade the substrate. The table below summarizes typical trends:

Grain Size Range (µm) Typical Electron Mobility (cm²/Vs) Conductivity Relative to Single Crystal
< 0.5 1–10 < 1%
0.5–5 10–50 1–10%
5–50 50–150 10–50%
> 50 150–300 50–90%

Note: Values are approximate for moderate doping (~10¹⁷ cm⁻³) and depend on defect density.

Manufacturing Methods to Control Grain Size

Controlling grain size during fabrication requires careful process design. The following techniques are commonly used:

Thermal Annealing

Post-deposition annealing at temperatures between 600°C and 1100°C promotes grain growth through solid-state diffusion. Longer anneal times and higher temperatures yield larger grains, but there is a trade-off with thermal budget, especially if the underlying substrate (e.g., glass or plastic) cannot withstand high temperatures. Rapid thermal annealing (RTA) can achieve large grains in seconds, limiting diffusion of dopants.

Seed Layer and Template Growth

Depositing a thin seed layer of crystalline silicon or using a foreign template (e.g., laser-crystallized amorphous silicon) can orient and enlarge grains. Excimer laser annealing (ELA) is widely used to produce polysilicon with grains up to several micrometers on glass substrates for thin-film transistors.

Doping and Impurity Influence

Dopants can either enhance or retard grain growth. Phosphorus and arsenic tend to accelerate grain growth, while boron can slow it. Additionally, impurities like oxygen or carbon can segregate at grain boundaries and pin them, limiting grain growth. Careful control of the ambient atmosphere during processing is essential.

Cooling Rate

In casting of multicrystalline silicon ingots for solar cells, the cooling rate from the melt determines the final grain size. Slow cooling allows grains to grow larger, but it also increases the risk of impurity segregation. Directional solidification techniques produce columnar grains that can be several millimeters wide, improving overall conductivity.

Applications in Solar Cells and Electronics

Polycrystalline Silicon Solar Cells

Most commercial solar panels today use multicrystalline silicon wafers with grains ranging from 0.1 mm to 10 mm. The average grain size directly affects the fill factor and efficiency of the cell. A study by the National Renewable Energy Laboratory (NREL) found that increasing grain size from 1 mm to 5 mm improved cell efficiency by approximately 1% absolute. This is a significant gain in the highly competitive solar industry.

However, grain size is only one of many factors. Passivation of grain boundaries, via hydrogenation or dielectric coatings, can mitigate the negative effects of small grains. Therefore, manufacturers often optimize both grain size and passivation simultaneously.

Thin-Film Transistors (TFTs)

In display technology, polysilicon TFTs are used in active-matrix liquid crystal displays (AMLCDs) and organic light-emitting diode (OLED) screens. Here, grain size uniformity is just as important as average grain size. Non-uniform grain sizes lead to variations in threshold voltage and drive current across the display, causing visible mura. Excimer laser annealed polysilicon typically produces grains of 0.3–1 µm, which is a trade-off between performance and uniformity.

Integrated Circuit Interconnects and Contacts

Polysilicon is also used as a gate electrode and local interconnect in CMOS technology. While grain size has been optimized for decades, modern nanoscale devices use polysilicon with grains that are often smaller than the gate length. This leads to increased resistance and variability, which is why many advanced nodes have moved to metal gates. Nevertheless, polysilicon remains important for certain memory and sensor applications.

Future Directions and Open Questions

Research continues to push the boundaries of grain size control. Emerging techniques include:

  • Selective epitaxy and nanostructuring—creating grains with specific orientation to minimize boundary effects.
  • Machine learning for process optimization—using AI to predict the relationship between annealing parameters and final grain size distribution.
  • Grain boundary engineering—tailoring the atomic structure of boundaries to reduce trap density, for instance by introducing coherent twin boundaries that have lower electrical activity.

One open question is the role of grain size in next-generation tandem solar cells where polysilicon is used as a bottom cell. In such devices, longer diffusion lengths (enabled by larger grains) are crucial for collecting carriers generated by infrared light.

Conclusion

The grain size of polycrystalline silicon is a fundamental parameter that governs its electrical conductivity. Larger grains reduce the density of grain boundaries, lower potential barriers, and increase carrier mobility, leading to higher conductivity. While the maximum possible grain size is limited by manufacturing constraints and cost, ongoing improvements in annealing techniques, seed layers, and passivation are closing the gap between polysilicon and monocrystalline silicon. For engineers and researchers working on solar cells, displays, or integrated circuits, understanding and controlling grain size remains a key lever for enhancing device performance. The interplay between grain size, doping, and grain boundary traps will continue to be a rich area of investigation as the demand for efficient, affordable silicon-based devices grows.

Further reading: For a comprehensive review, consult this 2004 review on polysilicon thin-film transistors or the classic text Polycrystalline Silicon for Integrated Circuits and Displays by T. I. Kamins.