Introduction

Modern high-speed electronics demand ever-increasing signal routing density while maintaining uncompromised signal integrity. As devices shrink and data rates climb into the tens of gigabits per second, traditional through-hole vias and even conventional blind/buried vias become bottlenecks in both layout density and electrical performance. Microvias—tiny laser-drilled vias less than 150 micrometers in diameter—have emerged as a critical enabling technology. By dramatically reducing the physical footprint of interlayer connections and minimizing parasitic capacitance and inductance, microvias allow designers to pack more high-speed signal paths into a smaller area without degrading signal quality. This article explores the fundamentals of microvias, their advantages for high-speed routing, manufacturing considerations, design best practices, and their expanding role in advanced electronics such as 5G infrastructure, aerospace systems, and high-performance computing.

What Are Microvias?

Microvias are small vias, typically defined by the IPC standard as having a diameter of 150 µm or less. They are formed using laser drilling (typically CO₂ or UV), which creates clean, precisely located holes through thin dielectric layers. Unlike mechanically drilled vias, which are limited to larger diameters and can generate burrs or smear, laser drilling produces smooth, well-defined via walls that enhance plating uniformity and reliability.

Microvias come in several configurations used in high-density interconnect (HDI) designs:

  • Stacked microvias – aligned directly on top of one another through multiple layers, creating a vertical connection path that resembles a continuous column. Stacked microvias offer the densest routing but require careful reliability assessment due to mechanical stress concentration.
  • Staggered microvias – offset from one another layer to layer, usually spaced apart horizontally. This structure reduces stress and is easier to manufacture, though it consumes slightly more area.
  • Skip vias – only connect non-adjacent layers by skipping intermediate layers (e.g., from layer 1 to layer 3). These are rarely used in high-speed designs because of increased via stub length affecting signal integrity.

In modern HDI PCBs, microvias are often combined with buried vias and through-holes to achieve high layer counts while maintaining thin, compact form factors. They are typically fabricated in sequential lamination cycles, with each laser-drilled layer pair added to a growing stack.

Advantages of Microvias for High-Speed Signal Routing

Increased Routing Density

The most obvious benefit of microvias is their small size, which frees up real estate on the board for additional traces and vias. A 100 µm microvia occupies less than half the area of a typical 250 µm mechanical via, and the annular ring can be reduced proportionally. This allows designers to route multiple high-speed differential pairs through a dense BGA fanout region where even a single traditional via would block several channels. In complex designs like application-specific integrated circuit (ASIC) packages or field-programmable gate array (FPGA) breakouts, microvias can increase routing density by 50% or more compared to conventional approaches.

Improved Signal Integrity

Microvias inherently improve signal integrity through several mechanisms:

  • Reduced parasitic capacitance and inductance – The smaller via barrel and shorter length lower capacitive loading and inductive reactance, preserving rise times and reducing reflections. Above 5 Gbps, the parasitic effects of even a short via stub become significant; microvias minimize these parasitics.
  • Shorter and more direct signal paths – With microvias, signals can transition between layers with less detouring. A direct, short path lowers insertion loss and reduces the risk of mode conversion in differential pairs.
  • Better impedance control – The small via geometry makes it easier to match the via structure to the characteristic impedance of the transmission line (typically 50 Ω single-ended or 100 Ω differential), reducing discontinuities that cause jitter and intersymbol interference.
  • Minimized via stubs – Stacked microvias eliminate long stubs that can resonate and create notches in the frequency response. In high-speed designs (e.g., 28 Gbps and above), even a few picoseconds of stub delay can degrade the eye diagram.

Enhanced Reliability

Laser-drilled microvias provide superior hole wall quality compared to mechanical drilling. There are fewer resin smear and glass fiber protrusions, which improves the copper plating adhesion and reduces voids. Additionally, because microvias are often part of a sequential lamination process, the epoxy resin used in the prepreg layers can be optimized for low coefficient of thermal expansion (CTE), matching the copper drill—a key factor in withstanding temperature cycling. Multiple reliability studies (e.g., IPC-TM-650) have shown that properly designed microvias with adequate copper thickness can survive thousands of thermal cycles without failure.

Thermal Management Advantages

Though often overlooked, microvias also contribute to thermal performance. By allowing direct vertical heat paths from hot components (such as processors and power amplifiers) to internal copper planes and heat sinks, microvias can reduce thermal resistance. Their high density enables more vias per unit area to conduct heat away from localized hot spots, improving overall thermal dissipation in high-power designs.

Impact on High-Speed Signal Routing

Return Path and Discontinuity Management

At high frequencies, maintaining a solid return path beneath a signal trace is critical. When a signal transitions between layers, the return current must also shift, and any discontinuity—such as a gap in the reference plane—creates common-mode noise and increases radiation. Microvias, because they are small and can be placed very close to signal vias, allow designers to place ground microvias adjacent to signal vias to provide a short, low-inductance return path. This technique, often called "via stitching," is essential for frequencies above 10 GHz. In dense BGA regions, microvia arrays can be arranged to form coaxial-like transitions, dramatically reducing parasitic effects.

Differential Pair Routing

High-speed serial links (e.g., PCIe Gen 5/6, USB4, 100G Ethernet) rely on tightly coupled differential pairs. Microvias allow the two lines of a pair to transition layers together with matched lengths, minimizing skew. The small via diameter also makes it possible to keep the via pair close to the same spacing as the differential traces, preserving the impedance profile. When using stacked microvias, the via pair can be symmetrical, further reducing common-mode conversion. Many simulation tools now include microvia models to predict performance; close correlation with measured data confirms the superiority of microvia‑based transitions over those using conventional vias.

Material Choices and Their Effect on Microvia Performance

The dielectric material surrounding a microvia strongly influences its electrical characteristics. Low-loss materials (such as Rogers 3000/4000 series, Panasonic Megtron, or ITEQ IT-968) are preferred for high-frequency boards because they offer low dissipation factor (Df) and stable dielectric constant (Dk) across frequency. However, these materials often have different flow and curing characteristics, which impact laser drilling efficiency and plating adhesion. For microvia reliability, the material must have low CTE in both x‑y and z‑axes to prevent barrel fractures during thermal cycling. Some advanced materials combine a low‑loss resin matrix with a very thin glass reinforcement to meet the tight dimensional requirements of sequential lamination. Designers should collaborate closely with fabricators when selecting materials for microvia‑based HDI boards that must operate above 20 Gbps.

Design Considerations for Microvia Implementation

Layer Stackup Planning

A successful microvia design begins with a well‑thought‑out stackup. The number of microvia layers, their position relative to core and prepreg layers, and the via stack strategy (stacked vs. staggered) must be defined early. For very high density, stacked microvias can be used in multiple sequential laminations (e.g., three or more microvia layers per side). However, each additional lamination cycle increases cost and potential for yield loss. A common approach is to use one or two microvia layers on each side for fanout of fine‑pitch BGAs, with conventional through‑hole vias for lower‑speed signals and power distribution.

Via Size, Pad, and Land Patterns

IPC‑6012 defines the minimum microvia pad size as via diameter + 75 µm annular ring (total pad diameter = via diameter + 150 µm). For a 100 µm microvia, the pad would be 250 µm. However, with advanced laser drilling and plating, some fabricators can achieve annular rings as small as 50 µm, allowing even tighter densities. The capture pad on the target layer must be at least as large as the microvia diameter plus the registration tolerance. Designers working with ultra‑fine pitch (0.4 mm or below) often need to reduce pad sizes to fit under the BGA footprint. In such cases, a via‑in‑pad (VIP) technique is used, where the microvia is placed directly in the surface pad. VIP requires careful filling with non‑conductive or conductive epoxy to avoid solder wicking and voiding.

Via Filling and Planarization

To support subsequent lamination layers, microvias are typically filled with an epoxy‑based material (non‑conductive) or copper plating (conductive). Filled vias provide a flat surface for the next layer’s pads and prevent air entrapment. Copper‑filled microvias offer the lowest electrical resistance and best thermal conductivity, but the filling process is more challenging and costly. Non‑conductive fill is adequate for most signal vias but may introduce a slight discontinuity in the return path. For high‑speed signals where via inductance is critical, copper‑filled microvias are recommended, especially for stacked configurations.

Signal Integrity Simulation and Validation

Given the complexity of microvia structures, pre‑layout simulation using 3D electromagnetic solvers (e.g., Ansys HFSS, CST, or Keysight EMPro) is essential for designs above 10 Gbps. The simulation must include the via barrel, pad, anti‑pad, and the surrounding dielectric material. S‑parameter results, TDR (time‑domain reflectometry), and eye diagram analysis will reveal impedance mismatches and resonant frequencies. Design rules derived from simulations can then be applied: for example, limiting the number of stacked microvias in a signal path to two, or requiring a ground microvia within 0.5 mm of every differential signal via. Production‑level validation through test coupons on the panel is recommended to verify that the microvia process meets electrical performance targets.

Manufacturing Process and Capabilities

Laser Drilling

The cornerstone of microvia fabrication is the laser drill. CO₂ lasers have been traditionally used for drilling microvias in reinforced epoxy materials (e.g., FR‑4), but for very small diameters (below 75 µm) or for certain resin systems, UV lasers offer better precision. UV lasers are also less damaging to the surrounding material and produce smaller heat‑affected zones. However, UV drilling is slower, leading to higher cost. Many fabricators now employ a combination: CO₂ for larger microvias and UV for the smallest pitch requirements. Aspect ratios (depth : diameter) for microvias are typically kept below 1:1 to ensure uniform copper plating, though some advanced processes achieve 1.5:1 with special plating chemistries.

Plating and Metallization

After drilling, holes are cleaned to remove debris and smeared resin (desmear step), then a thin seed layer of electroless copper is deposited. This is followed by electroplating to build up copper thickness. For microvias, even in small holes, the electrolytic plating must be controlled to avoid necking or voids in the via barrel. Uniform current distribution across the panel is critical; some fabricators use pulse plating or periodic reverse plating to achieve consistent copper coverage. Typical finished copper thickness in the microvia barrel is 15–25 µm, though thinner may be used for cost reduction. For high‑reliability applications (aerospace, military), 25 µm is preferred.

Inspection and Testing

Microvia quality is verified by cross‑sectioning (destructive) and by electrical reliability tests such as isothermal aging and thermal cycling (e.g., IPC‑TM‑650 2.6.8). Automated optical inspection (AOI) can confirm via presence and alignment, but cannot detect hidden voids. X‑ray laminography is sometimes used to inspect stacked microvia chains. For high‑volume production, statistical process control (SPC) on drilling and plating is maintained to ensure consistent yields.

Challenges and Mitigations

ChallengeMitigation
Reliability under thermal cycling
Stacked microvias can develop barrel cracking if the plating is too thin or if the CTE mismatch is high.		 Use copper‑filled vias with aspect ratio ≤ 1:1; select low‑CTE dielectric materials; limit stack count to 3–4 microvias; consider staggered stacking for high‑reliability designs.
Cost
Each lamination cycle adds cost; laser drilling is more expensive than mechanical drilling.		 Optimize the number of microvia layers to meet routing density needs without over‑engineering; combine microvias with conventional vias for non‑critical nets; use panel‑sized layouts to maximize utilization.
Testability
Fine‑pitch microvias make bed‑of‑nails testing difficult; flying probe testing becomes slow.		 Design for testability by incorporating test points on surface layers; use built‑in self‑test (BIST) for high‑speed nets; consider JTAG boundary scan for digital circuits.
Noise Coupling
Dense via arrays can create unintended electromagnetic coupling between nets.		 Use via guards (ground vias) around sensitive signals; maintain sufficient clearance between via pads on same layer; simulate crosstalk using 3D EM tools.

Applications Across Industries

5G and Wireless Infrastructure

5G base stations operate at frequencies from 3.5 GHz to 39 GHz, demanding PCBs with low loss, high isolation, and extremely dense routing for massive MIMO arrays. Microvias are used in the RF front‑end modules and digital backplane, often in combination with low‑loss materials like Megtron 6 or Rogers 4350B. The ability to stack microvias under a 0.5 mm pitch BGA for the baseband processor allows integration of many signal pairs without signal degradation.

High‑Performance Computing (HPC) and AI Accelerators

Modern AI chips (GPUs, TPUs) use interposers with microvia density exceeding 100 vias per square inch. These devices require hundreds of high‑speed connections to memory (HBM2/3) and network interfaces. Microvias enable the fanout of these fine‑pitch arrays while maintaining signal integrity at data rates of 28 Gbps and beyond. Many HPC motherboards also employ microvias for the PCIe Gen 5/6 traces to the CPU.

Aerospace and Defense

Radar systems, electronic warfare, and satellite communications rely on HDI boards with microvias for size, weight, and power (SWaP) reduction. The reliability of microvias under vibration and temperature extremes is well‑established, with military standards like MIL‑PRF‑31032 providing guidelines. Copper‑filled microvias are preferred for their thermal and electrical performance in both RF and digital domains.

Medical Electronics

High‑resolution imaging systems (ultrasound, MRI) use dense PCBs to process analog signals from thousands of transducer elements. Microvias allow the layout to fit within tight form factors while preserving signal fidelity. The low parasitic inductance of microvias is especially important for the analog front‑end circuits operating at tens of megahertz.

Comparison with Traditional Via Technologies

  • Through‑hole vias – Large (≥ 300 µm), mechanically drilled, used for power and ground distribution or low‑speed signals. They occupy significant board area and create long stubs that are unacceptable at high speeds. Microvias replace them in high‑density areas.
  • Blind vias – Mechanically drilled from one surface to an internal layer, typically with larger diameters (≥ 200 µm). They provide some density improvement but not the fine pitch of microvias. Blind vias often require filling to avoid voids in later lamination.
  • Buried vias – Connect internal layers, usually mechanically drilled. Offer moderate density improvements but still larger than microvias. For high‑speed designs, buried vias are used for non‑critical nets while microvias handle the high‑speed signals.

Microvias are essential when via pitch needs to fall below 0.8 mm, especially for BGAs with 0.5 mm pitch or smaller. In these cases, traditional vias cannot be placed between pads, forcing designers to use microvias in the pads themselves (VIP).

The evolution of microvia technology continues in several directions:

  • Ultra‑small vias (<50 µm) – Achievable with UV laser drills and advanced dielectrics, enabling even higher routing density for future 3D packaging and chip‑last substrates.
  • Copper‑filled stacked microvias for 3D IC substrates – As heterogeneous integration advances (chiplet architectures), microvia interposers will connect multiple dies with extremely low latency and high bandwidth.
  • Embedded components – Microvias combined with recessed passive and active components inside the PCB will further reduce assembly height and improve signal integrity.
  • Additive manufacturing – Inkjet or Aerosol Jet printing may replace laser drilling for very‑low‑ cost, flexible microvias in wearable and IoT devices, though current performance is still below that of laser‑drilled microvias.

As data rates push toward 112 Gbps and beyond, microvias will remain a critical tool for signal routing, but they will increasingly be used in conjunction with other advanced interconnect technologies such as embedded waveguides and optical interconnects for ultra‑high bandwidth.

Summary

Microvias have transformed high‑speed PCB design by providing a compact, electrically superior method for layer transitions. Their ability to increase routing density, reduce parasitics, and maintain signal integrity makes them indispensable for modern electronics ranging from 5G infrastructure to AI accelerators and defense systems. While manufacturing complexity and cost are higher than for conventional vias, careful design planning, material selection, and close collaboration with fabricators yield reliable, high‑performance boards. By understanding the nuances of microvia types, stacking strategies, and simulation requirements, engineers can unlock density and performance that were previously unattainable with traditional via technologies. As the industry moves toward even higher data rates and greater integration, microvias will continue to play a central role in the evolution of high‑speed electronics.

External references: For deeper technical details, see IPC standards IPC‑2226 and IPC‑6012. A comprehensive study on microvia reliability can be found in "Microvia Reliability in High‑Density Interconnects" by DPK. For material properties, refer to Rogers Corporation for low‑loss laminates. Practical design guidelines are available from Mentor Graphics (Siemens). Industry trends are discussed in “Microvia Advances for 5G and AI” on EE Journal.