How to Calculate Propagation Delay and Rise Time in Multiplexer Circuits

Understanding Propagation Delay and Rise Time in Multiplexer Circuits

Multiplexer (MUX) circuits are fundamental building blocks in digital systems, used to select one of several input signals and forward it to a single output. Precise timing analysis is critical when designing high-speed data paths, clock distribution networks, or communication interfaces. Two of the most important timing parameters engineers must master are propagation delay and rise time. This article explains what these parameters mean, how to calculate them, the factors that influence them, and how they interact in real-world multiplexer designs. Whether you are working with simple 2:1 MUXes or large fan-in multiplexer trees, understanding these metrics ensures reliable signal integrity and proper system operation.

What Is Propagation Delay in a Multiplexer?

Propagation delay (t_pd) is the time it takes for a change at the input of a multiplexer to appear at its output. More formally, it is the interval between a specified voltage threshold on the input signal (typically 50% of the logic swing) and the corresponding threshold on the output signal. Because multiplexers have multiple inputs (data inputs and select lines), the propagation delay can differ depending on which input path is activated. Manufacturers usually specify two values in a datasheet:

• t_PLH – delay from a low-to-high transition at the input to a low-to-high transition at the output.
• t_PHL – delay from a high-to-low transition at the input to a high-to-low transition at the output.

These values are not always symmetrical due to differences in the pull-up and pull-down drive strengths of the output stage. In high-speed CMOS multiplexers, t_PLH and t_PHL may differ by several hundred picoseconds. For reliable timing closure, both values must be considered.

Propagation delay is often grouped into two categories:

• Data-to-output delay: The delay from a change on one of the data inputs (with the select lines stable) to the output.
• Select-to-output delay: The delay from a change on the select lines (with the data inputs stable) to the output.

In many standard logic families, the select-to-output delay is slightly longer because it involves internal decoding logic. Always check the datasheet for both specifications.

Why Propagation Delay Matters

Excessive propagation delay limits the maximum clock frequency of a system and can cause race conditions or setup/hold violations in sequential logic. In multiplexer-based data paths, propagation delays accumulate along the longest path, ultimately determining the critical path that defines the system’s operating speed. Engineers use propagation delay data to perform static timing analysis (STA) and ensure that all timing constraints are met.

Calculating Propagation Delay in Multiplexer Circuits

The simplest way to obtain propagation delay is from the manufacturer’s datasheet. However, if you need to estimate the delay for a custom multiplexer design or for a simulation, you can model it using the internal RC time constants. A common formula for propagation delay in a CMOS multiplexer is:

t_pd = 0.69 × R_on × C_load

Where:

• R_on is the on-resistance of the pass-gate transistors (or the equivalent resistance of the output stage, typically 10–100 Ω for modern CMOS).
• C_load is the total load capacitance on the output (including the next gate input capacitance, wiring capacitance, and any parasitic capacitance).

The factor 0.69 comes from the 50% threshold (ln(2) ≈ 0.693) for a first-order RC step response. This approximation works well for digital CMOS circuits where the output transitions between voltage rails.

For a more precise calculation, the average propagation delay is defined as:

t_pd(avg) = (t_PLH + t_PHL) / 2

This average is often used in timing models when the exact waveform symmetry is not critical. In high-speed designs, however, the worst-case (larger) value must be used for setup time analysis, and the best-case (smaller) value for hold time analysis.

Example Calculation

Assume a standard 74HC151 8-input multiplexer. From the datasheet, typical values at 5 V supply and 25°C are t_PLH = 14 ns and t_PHL = 15 ns. The average propagation delay is:

t_pd(avg) = (14 + 15) / 2 = 14.5 ns

If the load capacitance is 50 pF (typical for PCB traces and one fan-out), and the output on-resistance is approximately 50 Ω, the RC model gives:

t_pd ≈ 0.69 × 50 × 50 × 10^-12 = 0.69 × 2.5 × 10^-9 = 1.725 ns

The large discrepancy between the datasheet value (14.5 ns) and the simple RC model (1.725 ns) highlights that actual propagation delay is dominated by internal gate delays (transistor switching, internal parasitics, and driver strength) rather than just the output RC load. The RC model works best after the internal logic has already been accounted for; in practice, rely on datasheet values or post-layout simulations.

What Is Rise Time in a Multiplexer Output?

Rise time (t_r) is the time required for the output signal to transition from a low voltage level to a high voltage level. By convention, it is measured between the 10% and 90% points of the signal amplitude (sometimes 20% to 80% for ECL logic). For a multiplexer, the rise time determines how quickly the output settles to a valid logic high after the input changes. Fast rise times are desirable for high-speed operation, but excessively fast edges can cause overshoot, undershoot, and EMI issues.

Rise time is closely related to the bandwidth of the multiplexer’s output driver and the load capacitance. It can be approximated using the same RC time constant model:

t_r ≈ 2.2 × R_on × C_load

The factor 2.2 comes from ln(0.9/0.1) ≈ 2.197. This relationship shows that rise time is about 3.2 times the propagation delay (since 2.2 / 0.69 ≈ 3.2) for a single-pole system:

t_r ≈ 3.2 × t_pd (for first-order RC response)

In practice, the ratio can vary because multiplexers have more complex internal circuits (multiple stages, non-linear drive). However, the approximate ratio is a useful rule of thumb for initial estimates.

Example Rise Time Calculation

Using the earlier 74HC151 example with t_pd ≈ 14.5 ns:

t_r ≈ 3.2 × 14.5 ns = 46.4 ns

Data from the 74HC151 datasheet lists typical rise time at 5 V as about 13 ns (10% to 90% with 50 pF load). The discrepancy again shows that the simple model underestimates internal driver behavior; datasheet values are more accurate. For a custom design using a fast analog switch MUX (e.g., the DG419), the rise time might be in the nanosecond range.

Factors Affecting Propagation Delay and Rise Time

Both propagation delay and rise time depend on multiple physical parameters:

Supply Voltage (V_DD)

In CMOS logic, higher supply voltage reduces on-resistance and increases drive current, thus reducing both propagation delay and rise time. For example, the 74LVC family operates at 3.3 V, but its propagation delay is longer than at 5 V. Temperature also affects carrier mobility; higher temperature increases resistance, increasing delays.

Load Capacitance

As seen in the RC model, both t_pd and t_r are directly proportional to the load capacitance. Each additional gate input or longer PCB trace adds capacitance. Designers must consider the fan-out and wiring load to avoid excessive rise times.

Input Transition Time

Slow input edges can increase propagation delay because the internal switching threshold is reached later. Most multiplexer datasheets specify input transition times (e.g., ≤ 6 ns for HC logic). Exceeding these limits can cause erratic behavior and increased power consumption.

Internal Architecture

Larger multiplexers (e.g., 16:1 versus 2:1) require more complex decoding, resulting in longer propagation delays. The number of pass-gate stages and the buffering strategy greatly affect both speed and rise time. Tree-type multiplexers typically have lower delay than single-stage implementations.

Measuring Propagation Delay and Rise Time

Accurate measurement requires a high-bandwidth oscilloscope and careful probing. Follow these steps:

1. Apply a known input signal with fast edges (rise time < 1/5 of expected output rise time) to avoid measurement error.
2. Set the oscilloscope input impedance to 1 MΩ for low-frequency MUXes or 50 Ω for high-speed (RF) MUXes. Use a 10× probe with low capacitance.
3. Define voltage thresholds: use 50% of V_DD for delay and 10%/90% for rise time. Most oscilloscopes allow setting these measurement points automatically.
4. Record t_PLH and t_PHL by measuring between the input and output at the 50% points. Average several transitions for statistical accuracy.
5. Measure rise time between the 10% and 90% points. Ensure the output signal is clean; any ringing or noise will distort the measurement.

For more advanced analysis, consider using a Time Domain Reflectometer (TDR) or a vector network analyzer (VNA) to extract the step response and derive both delay and rise time.

Relationship Between Propagation Delay and Rise Time

While they are often used together, these parameters measure different things: propagation delay is a time offset between input and output, whereas rise time is a transition duration. In a simple RC circuit, they are related through the time constant, but real multiplexers introduce additional delays from internal logic gates. Consequently, a multiplexer can have a very fast rise time but a long propagation delay if there are many internal gates before the final driver. Conversely, a multiplexer with short propagation delay (e.g., using a fast current-mode logic) might still have a relatively slow rise time if the output driver is weak.

For design purposes, both must be considered. In synchronous systems, propagation delay impacts setup and hold margins, while rise time affects the exact moment when the receiving gate sees a valid logic level. A slow rise time combined with a long propagation delay can cause the output to cross the switching threshold later than expected, reducing timing slack.

Practical Considerations for High-Speed Multiplexer Design

When using multiplexers in high-frequency or high-speed digital circuits, keep these guidelines in mind:

• Select the right logic family: For >100 MHz operation, use Advanced High-Speed CMOS (AHC), Low-Voltage CMOS (LVC), or Advanced BiCMOS (ABT). For very high speeds (several GHz), consider CML or ECL multiplexers.
• Minimize load capacitance: Place the MUX close to the driven gate. Avoid long, thin PCB traces. Use controlled impedance routing for 50 Ω environment.
• Manage select line timing: The select lines must be stable before the data changes to avoid glitches on the output. The setup time of the MUX (t_SU) must be satisfied.
• Use bypass capacitors: High-speed switching causes current spikes. Place 0.1 µF and 1 µF capacitors close to each MUX power pin to reduce supply noise that can alter delays.
• Simulate with extracted parasitics: Post-layout simulation using SPICE models of the actual multiplexer and interconnect is essential for accurate delay and rise time prediction.
• Consider temperature and supply voltage variations: Design for worst-case delay (low voltage, high temperature, slow-slow process corner) to ensure timing closure across all conditions.

Conclusion

Calculating propagation delay and rise time in multiplexer circuits is a fundamental skill for digital system designers. While datasheet values provide the most reliable numbers, understanding the underlying RC model helps in making quick estimates and identifying the impact of load capacitance and supply voltage. The relationship between propagation delay and rise time is not fixed; each parameter gives different information about the circuit’s speed and signal integrity. By using appropriate measurement techniques, simulating with robust models, and following best practices for layout and decoupling, engineers can ensure that their multiplexer-based designs meet timing requirements even in demanding high-speed systems.

For further reading, refer to Texas Instruments’ application note on propagation delay and rise time, see Wikipedia’s comprehensive page on rise time, or study the Analog Devices article on multiplexer fundamentals. These resources provide deeper insights into the physics and practical measurement of these critical timing parameters.