Analog-to-digital converters (ADCs) are fundamental building blocks in modern electronic systems, bridging the analog and digital domains by converting continuous real-world signals into discrete digital representations. Their performance directly governs the accuracy, dynamic range, and overall fidelity of measurement, communication, and control systems. However, ADCs are inherently sensitive to disturbances on their power supply rails. Power supply noise—unwanted voltage fluctuations originating from internal or external sources—can introduce errors that compromise the converter's linearity, signal-to-noise ratio, and effective resolution. Understanding the mechanisms of power supply noise injection and implementing robust mitigation strategies is essential for engineers who demand precision in high-performance data acquisition, instrumentation, and communications applications.

This article examines the sources and characteristics of power supply noise, explores its impact on critical ADC performance metrics, and provides a comprehensive set of proven mitigation techniques to ensure reliable, high-fidelity conversion in mixed-signal systems.

Understanding Power Supply Noise

Power supply noise encompasses any unwanted deviation from the ideal constant DC voltage supplied to an ADC and its associated analog circuitry. These disturbances can be periodic, random, or transient, and they couple into the ADC through the power pins, substrate, or ground plane. To mitigate noise effectively, engineers must first recognize the types and origins of supply noise.

Types of Power Supply Noise

  • Ripple: Low-frequency periodic fluctuations typically at 50/60 Hz or harmonics of a switching regulator's fundamental frequency (100 kHz to several megahertz). Ripple is often sinusoidal and can be predicted from the power supply design.
  • Spikes and Glitches: Short-duration, high-amplitude transients caused by sudden current demands from digital logic switching, relay actuation, or electrostatic discharge. These events can inject charge directly into the ADC's sampling capacitor, causing conversion errors.
  • Broadband Noise: Random noise distributed across a wide frequency spectrum, often originating from thermal noise in resistors, semiconductor shot noise, or the noise floor of switching regulators. This noise reduces the ADC's achievable signal-to-noise ratio.
  • Digital Switching Noise: High-frequency noise generated by clock edges and data transitions in digital adjacent digital circuits. It couples capacitively or inductively into the analog supply and ground lines.

Sources of Power Supply Noise

Noise sources can be internal to the system—such as switching power converters, DC-DC regulators, clock generators, and digital processors—or external, including electromagnetic interference (EMI) from nearby equipment, radio frequency signals, and mains hum. In mixed-signal systems where sensitive analog converters coexist with noisy digital logic, these sources create a challenging noise environment that demands careful design.

How Power Supply Noise Affects ADC Performance

Power supply noise degrades ADC performance through several direct and indirect mechanisms. The severity of the impact depends on the converter's architecture (successive approximation register, sigma-delta, pipeline, etc.), the noise frequency relative to the sampling rate, and the effective power supply rejection ratio (PSRR) of the device.

  • Increased Quantization Error and Missing Codes: Noise on the reference or supply voltage shifts the decision thresholds of the comparator(s) within the ADC. This can cause the converter to produce incorrect output codes, effectively reducing its resolution. In extreme cases, certain codes may be entirely skipped (missing codes), rendering the ADC non-monotonic.
  • Reduced Signal-to-Noise Ratio (SNR): Supply noise adds an error component to each sample that is uncorrelated with the input signal. This in-band noise raises the noise floor, directly degrading SNR. For every 1 dB increase in noise power, the effective number of bits (ENOB) decreases by approximately 0.5 bits, assuming a sinusoidal input.
  • Spurious-Free Dynamic Range (SFDR) Degradation: Periodic ripple or switching noise creates spurious tones in the ADC output spectrum. These tones can mask small signals and severely limit the SFDR, a critical metric in communications and spectrum analysis applications.
  • Sampling Time Jitter: Fluctuations on the internal voltage references or bias currents can modulate the sampling instant. This aperture jitter introduces a noise component proportional to the input signal slew rate, further limiting the achievable SNR at high input frequencies.
  • Increased Total Harmonic Distortion (THD): Nonlinearities caused by supply-induced modulation of the ADC's internal comparators or amplifiers generate harmonics of the input signal, increasing THD and degrading overall linearity.

Key Performance Metrics Affected

  • Effective Number of Bits (ENOB)
  • Signal-to-Noise Ratio (SNR)
  • Signal-to-Noise and Distortion (SINAD)
  • Spurious-Free Dynamic Range (SFDR)
  • DC Offset and Gain Error
  • Feedthrough and Crosstalk

Power Supply Rejection Ratio (PSRR) and Its Limitations

ADC datasheets often specify Power Supply Rejection Ratio (PSRR), which quantifies how much supply noise couples to the output. PSRR is frequency dependent—typically high at DC but dropping off at higher frequencies due to limited bandwidth of internal circuits. For example, a high-performance 16-bit SAR ADC may have a PSRR of 80 dB at 100 Hz but only 40 dB at 1 MHz. Therefore, relying solely on the ADC's intrinsic PSRR is insufficient for suppressing high-frequency switching noise. External mitigation is almost always required to achieve full performance.

Common Sources of Power Supply Noise in Mixed-Signal Systems

In a typical mixed-signal PCB, several noise sources can compromise ADC performance:

  • Switching Regulators: Used for efficiency, they generate ripple at the switching frequency and its harmonics, along with high-frequency ringing due to parasitic inductance and capacitance.
  • Digital Processors and FPGAs: Draw large, rapid current spikes during clock edges, creating ground bounce and supply droop that feed into analog rails through shared impedance.
  • Clock Distribution Circuits: Produce periodic noise that can alias into the ADC passband if poorly filtered.
  • External Magnetic Fields: From transformers or motors induce currents in loops formed by power traces.
  • Ground Loops: Multiple return paths create potential differences between analog and digital grounds, injecting noise into the ADC's reference.

Mitigation Techniques for Power Supply Noise

Mitigating power supply noise requires a layered approach combining component selection, PCB layout, and filtering. Below are detailed techniques organized by implementation domain.

Decoupling and Bypass Capacitors

Placing ceramic capacitors with low equivalent series resistance (ESR) and inductance (ESL) close to the ADC power pins creates a low-impedance path for high-frequency noise to ground. Use multiple capacitors in parallel: a 0.1 µF capacitor for 10–100 MHz rejection, a 1 µF or 10 µF for lower frequencies, and a bulk tantalum or electrolytic capacitor (10–100 µF) farther away to handle transient currents. The total decoupling network should cover at least two decades of frequency beyond the ADC conversion rate. For best results, place the smallest capacitor closest to the pin, followed by larger ones in decreasing order of resonant frequency.

Low-Dropout Regulators (LDOs)

LDOs provide clean, low-noise DC voltage with high PSRR across a broad frequency range. A linear regulator following a switching regulator can attenuate ripple by 60–80 dB. Choose an LDO specified for noise-sensitive applications (e.g., Analog Devices LT3045 or Texas Instruments TPS7A47). Keep the output capacitor as recommended in the datasheet to maintain stability and transient response.

Power Supply Filtering

  • RC Filters: A series resistor with a capacitor to ground forms a low-pass filter. The resistor adds some voltage drop but can reduce ripple by 20–40 dB at frequencies above the cutoff. Use low-inductance resistors and X7R or C0G capacitors.
  • LC Filters (Pi Filters): An inductor with capacitors on both sides provides high attenuation with acceptable DC resistance. Ferrite beads can be used for high-frequency noise suppression, but they saturate at high DC currents and may introduce nonlinearities.
  • Active Filters: Op-amp based filters (Sallen-Key, multiple feedback) can provide sharp cutoff and high Q, but they require additional power and can add their own noise.

Proper Grounding and PCB Layout

Ground is the return path for all circuit currents; any impedance creates a voltage that appears as noise. Best practices include:

  • Use a continuous, low-impedance ground plane under the ADC and analog circuitry. Avoid splitting the ground plane except under digital-only areas, and use a solid plane for mixed-signal sections.
  • Route analog and digital signal traces separately and avoid crossing them over each other. If crossover is unavoidable, use a ground plane between layers.
  • Keep the ADC's analog ground (AGND) and digital ground (DGND) separate on the schematic but connect them at a single point (star ground) close to the ADC, often on the ground plane itself.
  • Minimize trace lengths between the supply output, decoupling capacitors, and the ADC power pin to reduce series inductance.

Separate Power Domains

Isolate the analog supply from the digital supply using individual LDOs or separate regulator outputs. Use ferrite beads or small resistors to create a physical partition between planes. This prevents digital switching currents from modulating the analog supply rail. Additionally, provide separate return paths—analog return currents should not share traces with digital return currents downstream of the star ground.

Shielding and Layout Optimization

Physical shielding with metal cans or copper planes can reduce electromagnetic interference. On the PCB, place the ADC and its analog circuitry away from high-speed digital buses (e.g., DDR memory, high-speed serial links). Use guard rings around analog traces and connect them to the analog ground plane. For very high-speed ADCs (sample rates above 100 MSPS), consider using differential signaling for clocks and data outputs to reject common-mode noise.

Power Supply Sequencing

Many high-performance ADCs require multiple supply voltages (analog, digital, I/O). Improper sequencing can cause latch-up, excessive inrush current, or internal damage. Follow the manufacturer's recommended sequence—typically analog supply before digital supply. Use a dedicated power sequencer IC or simple RC delays with MOSFETs to ensure rails ramp up and down in the correct order.

Active Noise Cancellation

For extreme noise requirements, active feed-forward or feedback cancellation circuits can subtract known noise patterns from the supply rail. This technique is more common in laboratory-grade instruments but may be justified in high-end medical imaging or radar receivers. An injection transformer or a high-PSRR LDO with a noise cancellation pin can provide additional rejection at specific frequencies.

Best Practices for ADC Power Supply Design

The following checklist summarizes actionable steps for minimizing power supply noise in ADC systems:

  • Select ADCs with high PSRR and wide bandwidth; review the PSRR vs. frequency plot in the datasheet.
  • Use low-noise LDOs for analog rail generation; avoid switching regulators directly powering ADCs unless followed by an LDO and noiseless filtering.
  • Place decoupling capacitors as physically close as possible to the ADC power pins, using multiple values (e.g., 100 pF, 1 nF, 0.1 µF, 10 µF).
  • Implement a solid, continuous ground plane and use star grounding for analog and digital returns.
  • Separate analog and digital power domains with ferrite beads or isolation resistors.
  • Filter the ADC input reference voltage with a clean buffer or reference IC followed by a RC filter.
  • Minimize clock jitter by using a dedicated clean clock source and proper termination; clock noise couples through the power supply.
  • Simulate the power delivery network (PDN) for impedance and resonances before PCB fabrication.
  • Test the final design by measuring SNR and SFDR with and without supply noise injection to verify mitigation effectiveness.

Case Study: Improving SNR in a 16-bit Data Acquisition System

Consider a 16-bit SAR ADC sampling at 500 kSPS for a precision industrial control application. Initial prototypes showed an SNR of 85 dB, well below the theoretical maximum of 96 dB. Investigation revealed excessive ripple (20 mV pk-pk at 600 kHz) from a switching regulator on the 5 V supply that powered the ADC's analog rail. The following changes were implemented:

  • Added a 3.3 V LDO (LT3045) after the switching regulator, providing 60 dB of ripple rejection at 600 kHz.
  • Installed a 2.2 Ω resistor in series with the 3.3 V line and a 47 µF tantalum capacitor to ground, forming a low-pass filter with a cutoff of approximately 1.5 kHz.
  • Replaced the 0.1 µF decoupling capacitor adjacent to the ADC with a 1 µF X7R and added a 10 nF C0G capacitor to improve high-frequency rejection.
  • Reduced the ADC's digital supply noise by adding a separate LDO and isolating the digital ground return with a ferrite bead.

After these changes, the measured SNR improved to 94 dB—close to the datasheet limit—and the residual noise floor dropped by 12 dB. The solution added minimal PCB area and component cost, demonstrating that systematic noise mitigation is both practical and effective.

Conclusion

Power supply noise is a pervasive challenge in ADC-based system design, directly impacting accuracy, dynamic range, and linearity. Its effects—ranging from missing codes and reduced SNR to spurious tones and timing errors—can undermine even the most carefully matched analog front-end. By understanding the frequency-dependent nature of PSRR and the coupling mechanisms of ripple, spikes, and broadband noise, engineers can implement a multi-tiered mitigation strategy. Decoupling capacitors, LDOs, proper grounding, separate power domains, and optimized PCB layout form the cornerstones of a noise-immune power supply. Additional techniques such as active filtering and careful sequencing further enhance performance in demanding applications. Through disciplined design and verification, it is possible to preserve the full intrinsic performance of modern high-speed, high-resolution ADCs, ensuring reliable data conversion in any electronic system.

For further reading on ADC power supply design and noise characterization, consult application notes from Analog Devices and Texas Instruments' guide to power supply rejection in ADCs.